Discuss some DQS

Hi all,
I just have some fun with DQS Strobe timing

The DQS signal has several characteristics:

DQS is bi-directional

A DQS line is typically generated for 8 lanes of data from the DDR memory

The phase of DQS relative to the data depends on the operation being performed (Write or Read)

DQS is not free running

In the memory device, DQS is generated by DLL to minimize the skew between it and data

DQS has a Preamble state just after the signal comes out of tristate where DQS goes low

DQS has a Postamble state just before returning to tristate where DQS goes low

So according to this, let see some real benches:

Testbed:
CPU : AMD FX55, Mach II cooled
Mainboard: DFI NF4 SLI-DR (BIOS 310)
OS: Windows xp
Ram: GSkill 1gb LE DC Kit
Video card: X850xtpe, Water cooled
PSU: OCZ power stream 600adj

**please note: in BIOS if you choose increase, that would show "slower" in A64tweaker ;if you set decrease in BIOS, A64tweakerwould show faster

First of all let's see DQS off:

http://www.ocxtreme.org/onepagebook/DQS/8m0.jpg

DQS slower ;skew:128, super pi 8m is a bit faster than off

http://www.ocxtreme.org/onepagebook/DQS/8m1.jpg

DQS faster; skew:128, it's slower than off.

http://www.ocxtreme.org/onepagebook/DQS/8m2.jpg

Summary:

DQS skew Control--->Increase for performance, and Decrease for Stability.

DQS Skew Value-->the value that is Increased or Decrease when you set the DQS skew control. This is not a very sensitive timing wecan try 50~248
Both are slight influence on bandwidt and stability.

Good find!
This is NF4 only ?
Nevermind just found out it worked for NF3

thanks OPB, im glad you brought up this DQS thing

hmm.. little Q .. how much do you gain in mem bandwidth? (with 128 slower)

:confused: currently i set my DQS Increase = 4 :p: (dunno what that means b4), so is smaller better/ worse? coz i see theres a lot of number to try (0-255) :p:

oh ya.. i use twinmoss Utt @ 3.3v for 24/7 and passed memtest 5# stable like a rock..(6 hours wall time or so)

nice for TREF 100mhz 1.95u corresponds to what in DFI NF4 bios ?

lol just try it myself... jist found out with 0.6 beta do not need to set mannualy from bios :stick:

BIOS 2/18

my sweet spot atm is DQS = 200

but it vary alot.. how bout yours?

PS: thats on fsb 250 2-2-2-5 , and loads of program running..

Quote:

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Originally Posted by eva2000

nice for TREF 100mhz 1.95u corresponds to what in DFI NF4 bios ?

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I think that is 3684.

Quote:

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Originally Posted by eva2000

nice for TREF 100mhz 1.95u corresponds to what in DFI NF4 bios ?

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you can find it in HERE

Quote:

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Originally Posted by AG

3684= 100mhz(1.95us)

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:toast:

bout time someone did this thanks onepage! :toast:

Great post

what about on the DFI NF3 board? what increases stability? increasing or decreasing the skew in bios? i thought rgone said increasing skew increased stability?

FYI...

What values are best depend on CPU, RAM, and MB used... no global generalization applies, even in regards to direction with respect to stability.

Bandwidth isn't affected by only changes to the DQS skew value. The perf benefit seen in some cases is a result of the data being available to the core earlier in the cycle. It doesn't affect the number of cycles per access (other than by possibly allowing tighter timing settings).

This is the same setting as "Skew Rate" in the DFI Infinity bios. This micro-adjusts the position of the clock rising/falling edge vs the actual data signal coming out of the DDR chips. It allows you to micro manage the actual point at which "data" is sampled by the memory clock, this can allow you to tune very precisely where the "sampling" of the data lines is relative to a theoretical center point.

The adjustment moves the EXACT point of data sampling of the datalines within a sub-clock cycle window to allow you to hit the nail on the head as far as WHEN precisely the data is VALID most accurately. This point can vary by DDR type, or qulaity of connectors, or %precision of ternimating resistors, etc etc. Literally hundreds of small contributions to improve/deprove the data signal coming out of the DDR chips onto the memory bus and over to the A64 DQ pins....128 of them.

Theorecticaly the sampling point would be X, but real world factors can make YOUR system's best point Y, so this lets you dial in.

Mind you, this cannot actually help you SPEED UP anything, it can simply help you find the MOST stable point of sampling the data pins. Once you maximize this, al the "timing" adjustments can then be tweaked into thier maximum points.

But the SKEW point is determined by the connectors, resistors, DDR chips, etc etc within a fixed window of the memory clock cycle..... it doesnt add/subtract waitstates or otherwise affect timing directly. But if the skew value is OFF you wont get stable data sampled at the highest speed/tightest timings otherwise possible.

EX: the 250Mhz clock, is 4ns cycle time. DDR is sampled on both edges, so a 2ns period per dataset. This skew lets you adjust in PICOSECONDS the precise point the data is sampled within the 2ns window. The digits 0-256 +/- prolly equate to 5-10 PICOSECONDS each of adjustment, I really dont know for sure. you have to read the A64 technical docs indepth to find out.

Good detailed explanation uwackme :toast: I was too lazy this morning to type that much :lol:

Just one small addition and one minor correction... in your "etc." list are two important factors - CPU itself (FX vs 90nm Winnie, etc.) and the temp of the average temp of the parts (settings for -100C vs water for example).

The minor correction - for DDR skew adjustment DLLs are used... Delay Lock Loops... they don't adjust skew by a fixed time value, they adjust skew by adjusting the phase of a signal (in this case the data strobe). The values are a percentage of the clock they are driven with. What percentage depends on the design and number of bits used. So the same DLL value at two different frequencies will result in two different delay values. One example are the DLL IP cores for ASICs that TSMC offers, in their 90nm process good for freqs up to 800+ Mhz and resolution in the tenths of a percent of the clock period :shocked:

Peace bro

OK, I have some questions...

1) Am I right in thinking that DQS alters where each data bit is sampled? So by changing its value we can get it to sample at the most stable part of the data bits... where they are most likely to have stabilised at either 1 or 0?

2) If what I said above is right, I guess selecting Increase & Value would mean the sampling is done "later" in each bit... so some kind of a delay is implemented in the AMD Memcontroller? Am I close?

3) So... If I AM on the right track I understand how we can "Increase" DQS, but what I don't get is how we can "Decrease" it?
Are the options "Increase"/"Decrease" relative to the MIDDLE of each data bit?
EG, the BIOS auto calculates the middle of each data bit based on the frequency, and tries to allocate a DQS value that will fall there... then if we select "Decrease" the value (I'm guessing a Timer/Counter preload value or something similar) will be reduced... moving the sampling closer to the previous clock edge?

If I am rambling please give me a virtual beeetch slap hehehe

Hi bro :toast:

Quote:

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Originally Posted by Rabbi_NZ

OK, I have some questions...

1) Am I right in thinking that DQS alters where each data bit is sampled? So by changing its value we can get it to sample at the most stable part of the data bits... where they are most likely to have stabilised at either 1 or 0?

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The edge of DQS is used to sample the data. By changing how far DQS is phase shifted by the DLL, you can achieve optimal alignment.

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2) If what I said above is right, I guess selecting Increase & Value would mean the sampling is done "later" in each bit... so some kind of a delay is implemented in the AMD Memcontroller? Am I close?

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See comment to #1 above... the DLL is what creates the phase shift... it is not a pure delay. Through the use of the DLL the DQS signal can be moved so that it occurs later or earlier. And yes, the DLL is in the memory controller resident in the CPU. (note, there is also one in the memory chip used to align the clock signals, but it is a self-adjusting DLL that you can't program).

Quote:

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3) So... If I AM on the right track I understand how we can "Increase" DQS, but what I don't get is how we can "Decrease" it? Are the options "Increase"/"Decrease" relative to the MIDDLE of each data bit?

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Yes, relative to the middle... although the DQS signal as it leaves the memory chip is actually aligned with the "edge" of the data "window".

Quote:

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EG, the BIOS auto calculates the middle of each data bit based on the frequency, and tries to allocate a DQS value that will fall there... then if we select "Decrease" the value (I'm guessing a Timer/Counter preload value or something similar) will be reduced... moving the sampling closer to the previous clock edge?

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No, there isn't any "autocalulcation" done by the BIOS. However, I would bet that Oskar is trying to tune the newer BIOS's RAM tables with some pretty good "default" values based on the type of RAM used. Note that when you set the DQS skew value, you are overiding the default value the BIOS sets it to.

The "starting point" (a zero value for skew) is basically a phase shift of 90 degrees. IF the DQS (data strobe) and DQ (data) signals arrived without any distortion, difference in transition time, etc., etc. then they would be optimally aligned with a value of 0. The adjustment is needed because in the real world, there are signal distortions, unequal delay paths, unequal loading, mismatches between termination values, etc.

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If I am rambling please give me a virtual beeetch slap hehehe

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As you wish :slap:

hehehehehehe :rofl: Not that I would ever ramble :wasntme:

Sometimes a pic is worth a thousand words... try this one out bro :D
http://img8.exs.cx/img8/4895/dqsskew1nz.th.png

Is there any way to measure how much you need to adjust it? The diagrams you drew look like waves and I started me thinking about more uses for my scope.

If you were just using waves as a representation tell me and I won't think about trying to measure them.

EMC2, big thanks for the help bro... been messing with DQS all day, trying to get MemTest Test #8 error free at 257 2-2-2 3.2vDimm... I am sooo damn close! hehehehe

I have another question... will DQS need to be changed when I change RAM frequency? EG, at 260+ 3.3vDimm I will no doubt have to retune it right?

Also, what d'you reckon bout it relating to Drive Strength?
The higher the drive strength the earlier a data bit can be sampled?

Tune in next week for the answers to these and many more great mysteries hehehhehe

Peace dude, cheers for all the help you give me :toast:

Fastest + 128 gives me -0'5s in pi 2MB ! that's good :) (on a MSI Neo 2)

First, stupid me forgot something important...

OPB, thank you for putting your info up and starting this discussion bro :toast:


--- Craig ---

If you have a good enough scope and probe set, yes you can use the info gained to help adjust DQS timing. You'll need something at least on the order of a TDS684 DSO or better a TDS78x DPO series scope though and matching quality probes (active, 1pF load)... and need to have access to the back of the board so you can instrument @the CPU socket. Also note that you will not be able to see your skew adjustments, as they are going on internally to the mem controller. The info gained would only tell you the eye size and relative starting positions of DQS vs the DQs. If all you are looking for is to do skew adjustments, really easier to simply use testing with the memory running "on the edge" (FSB pushed just to the point of a handfull of errs in T5).

No time this morning for generated pics, so here's a simulation of things from an outside source:

http://img8.exs.cx/img8/9628/ddrdataeye6xs.th.png


--- Rabbi ---

No problem man :) Re-tuning shouldn't be required with only frequency changes... remember the DLL works by phase shifting... relative position remains the same regardless of frequency. Tuning is best done at high frequency and "on the edge" timing.

Drive strength changes can affect it, especially the DIMM drive strengths... and of course different DIMMs do as well. If you look at that diagram I put up, the edge rates of the signals change with drive strength changes (as can signal reflections, overshoot, etc.). This can move the optimal point. So can Vmem/Vtt changes, though to a lesser extent if changes are in the upward direction. And lastly, Vcore changes can as well. Vmem/Vcore both affect speed and signal shape, Vtt affects the sampling point. No time for pics this morn, church, gotta run.

Peace bro :toast:

Hi, my a64 is stable under Prime95 (CPU/RAM) but when I use sp2004 version 0.30 the RAM produces an error after 6s, and it comes a warning in my systray which quotes the following: eventid:106/107 WMIxWDM ioLogMsg.dll.
I have set the RAM Time Settings according to one of the tutorials on this page (tccd ddr620 g.skill)

The DQS is INCREASE and DQS Value is 255, its possible that is the reason for my ERROR??

pls help me..thx