"WinBootInfo is the advanced Windows Boot Analyzer that logs drivers and applications loaded during system boot, measures Windows boot times, records CPU and I/O activity during the boot, and much more!"
http://www.clockmod.com/index.php?/p...nbootinfo_1.0/
I’ve started this thread to look in more detail at what happens during boot with a focus on trying to better understand the data flow relationship between the CPU and storage system.
I’ve noticed that the Interrupts and Context Switching change considerably between HDD & SSD. On HDD Total Interrupts are lower and Total Context Switches are higher when compared to SSD.
My first area of interest is to therefore understand the impact of the relationship between Total Interrupts and Total Context Switches and why they are so different depending on the speed of data flow.
Why would the CPU seem to max out more on a HDD during boot over a longer period when compared to booting from a SSD? I would have thought the faster flow of information from the SSD would have had the opposite effect. :confused:
The other area of interest is exactly why the amount of data transferred is so variable. I’ve seen a difference from 52MB to 337MB in the few examples posted so far in the hIOmon SSD Performance Monitor - Understanding desktop usage patterns thread. Is it due to the WINSXS folder that just seems to get larger and larger over time?
I’ve copied below the only info I could find that explains what an Interrupt and Context Switch is.
Interrupts
“Each component in the computer must have its own line of communication to the CPU for communication. This line is called an interrupt, or IRQ, line. Whenever you ask the CPU to process something, one of the computer’s components sends an interrupt message (a small electrical charge) to the CPU, asking it to process the information. The CPU will stop whatever it was doing and provide the peripheral with the requested information. While this process may appear to be cumbersome and unreliable, it actually works very well if configured correctly.
In today’s computers, the CPU has a single interrupt line. Since computers have many different components that need to communicate with the CPU, we now have the programmable interrupt controller (PIC). There are two PICs that control eight interrupt lines, giving the system a total of 16 interrupts.
If you are asking yourself how two PICs can talk to a CPU that only has one interrupt line, don’t worry. The two PICs are daisy chained, or cascaded, together. To illustrate this concept, pretend that you have two surge suppressors that have eight outlets apiece. The power cord on one of them is plugged into the wall outlet, just like the CPU has one interrupt line. The second surge suppressor is plugged into the second outlet of the first one, chaining them together and allowing both of the surge suppressors to provide power to fifteen outlets total”.
http://articles.techrepublic.com.com...1-5033794.html
Understanding Context Switches
“I don't want to go too much into details here, so this is only a very simple basic description of context switches but it should help you understand what it really means.
Processes contain "threads" that are doing the work; they are scheduled and run on the system CPU (at one CPU not on all available CPU's). A process can have multiple threads but only one thread can run on a CPU at a time. The amount of time a thread runs is called "quatum" and when the time is over the system "switches" to the next thread in line (This is the normal case for a switch) – a "context switch" happened.
If the performance counter shows high context switches, it means that threads have less time to do their work and the system performance might go down”.
http://www.thomaskoetzing.de/index.p...196&Itemid=260
Here is a boot up using screen using a QX6850 and an Intel SSD
http://img541.imageshack.us/img541/3862/85767738.jpg
Here is a screen shot of the difference between an old OS on HDD and a fresher OS on SSD. Notice the huge difference in read data on the older OS.
http://img577.imageshack.us/img577/2720/73614319.jpg