Regor, Istanbul Die's - personal impressions

Well, I was rather board this w/e. So I decided to get creative with K10.5 Dies . My inspiration here was A. I don't fully agree with Han's prediction on the Istanbul die.. I don't think they'll re-arange cores or L3 Tags in reality. and B. The Die size "leaks" for Regor @ 80mm2 seem too small to me..

So If the nerdier members wish to give solid input on this feel free.. this is what i've come up with so far:

Istanbul: Hexa Core,6x0.5Mb L2 1x 6Mb L3

Main differences Vs Han's impression are:-
A. Maintaining core 1-4 layout.. I don't think AMD would really have the time or resource to rearange the existing cores, and hence all their datapaths in realtion to the NB.. personal thought, feel free to disagree.
B. I've moved HT link's to the side of the core as per Han's impression, but have only moved some L3 tiles to fill the space. I have a feeling the area between the two L3 Cache sections are buffers, and moving them would be a pain in the arse. Also, on shanghai there are 4 distinct logic 'blocks' in the NB. To me they're some sort of register/interface to the induvidual cores, so I've added 2 more of them for good measure.

I've also added some 'random' Logic to the "left" side of the centrally located Northbridge/bus logic section to account for Istanbuls new HT snooping feature.. I'm assuming the extra real estate afforded by adding the cores allowed them to add this technology. So i've snuck it in there. Feel free to suggest otherwise..

http://img152.imageshack.us/img152/8...bulfinalcr.jpg


Regor: Dual Core 1Mb L2 x2

Here, I've essentially emulated the Griffin Layout with the exception of the single Full duplex HT link - I've copied K10's (not K10.5) method of running the HT link in 2 sections side by side behind the L2 (behind the L3 on K10).. reference the original K10 die for reference of what i'm talking about here. The extra space between cores I've used to widen the NB section. I've also removed 2 of the above mentioned NB sections from Shanghai/deneb, I feel they're related to each core so two wouldn't be needed. these are also the sections I moved to the sides to shorten and widen the NB section.

Anyway, as you can see I don't know how 80mm2 will be possible with these cores.. It seems the memory interface and HT Links DONT scale to well with process shrinks. They are Larger in scale with the core in comparison to 65nm. I also roughly tried combining the 2 "top" cores instead, but it still results in very similar ~100mm2 core size..

http://img152.imageshack.us/img152/8...orfinalpub.jpg

discuss!

kudos for thread... hopefully this will lure Hans to post his POV ;)

In the midtime here's how he depicted Istanbul:

http://www.dvhardware.net/news/amd_i...s_de_vries.jpg

I'm with Hans when it comes to die size... AMD must stay below 300 sqmm

Regarding the Regor, I don't see the point for AMD to create separate mask for Dual Core K10... it's reasonable to presume that Regor will be harvested Propus!

With that in mind, I'd like to see yours and Hans opinion on Propus die!

Quote:

---

Originally Posted by Nedjo

Regarding the Regor, I don't see the point for AMD to create separate mask for Dual Core K10... it's reasonable to presume that Regor will be harvested Propus!

With that in mind, I'd like to see yours and Hans opinion on Propus die!

---

They can't create Regor from Propus --> 2x1MB L2. So they designed a separate mask and they will use it as Regor, Caspian, Champlain, and Geneva.

http://www.techpowerup.com/reviews/A...images/26k.jpg

IMHO is that the separate mask is a logical step.

mAJORD, the highest I'd go for Regor would be 90-100mm^2.

It is clearly not a die aimed for multiple sockets, so cHTT links are probably not implemented at all (like Propos), saving up some edge space.


The thing is, according to my previous previous (really previous? :p:) estimations that took Hans' Deneb and Istanbul illustrations into practice, Regor would have taken ~170mm^2. I'm rather sure the 141mm^2 number is really close to accurate. So they are slimming down something else than just the cHTT pads, too. What about memory and the HT switch? Could be more optimized for space?



p/s: Are we 100% sure on the 6MB L3 for Istanbul, too?

p/p/s: @ Nedjo
Regor WILL exist as a seperate die. It is AMD's chance to get the nettop (desktop) and partially netbook market. Atom as it is now is still slightly too feeble to handle Win 7 and say, iTunes and browsing, or even gaming. The 1MB L2 is probably an experiment which IMHO should have been 512KB (enough for K8/10) but let's see how they handle it.

Yes, Regor will be very similar to Turion Ultra successor. I bet it will be same die but binned for low power or higher speeds.
It makes sense for AMD to do that, because they need reasonable good CPU for Laptop market and cheap chip for Desktop.

I like your die shoots mAJORD :up:

Quote:

---

Originally Posted by Macadamia

I'm rather sure the 141mm^2 number is really close to accurate. So they are slimming down something else than just the cHTT pads, too. What about memory and the HT switch? Could be more optimized for space?

---

I was quite surprised by such a small die size when you first brought it up.
If true then they must have made the middle area with the HT/memory switch
thinner (3 HT's less) and must have reduced some border area's.

Something like this:

http://www.chip-architect.com/news/A...s_Brisbane.jpg

The image is based on your 141 mm^2 estimate. The particular x & y dimensions
would allow exactly 6 chips/per mask. A mask illuminates in general an area
of max 26mm x 33mm. More area illuminated means higher production efficiency.


Regards, Hans

Hmm, speaking of which, when was the last time AMD made a consumer oriented die in the K8 era? AFAIK everything else was just server disabled. If there were one, I'd like to see how the HTT and NB add up.

I've got word on the die size, but I'm not sure if it's an official measurement or something done by someone else (since samples are up and around in partners' hands).


Hans, any more illustrations/predictions for Istanbul? If it's a 300mm^2 die it's almost certain that AMD will make this the volume part instead, harvesting to emulate Shanghai and Deneb SKUs (Deneb might be kept for high-speed chips if they intend to go down that road in the future).

Quote:

---

Originally Posted by Macadamia

Hans, any more illustrations/predictions for Istanbul? If it's a 300mm^2 die it's almost certain that AMD will make this the volume part instead, harvesting to emulate Shanghai and Deneb SKUs (Deneb might be kept for high-speed chips if they intend to go down that road in the future).

---

Good news is that the probe filter is enabled and working. I think I remember
a roadmap where this functionality was only enabled in Sao Paulo. Using a
(software adjustable) part of the L3 caches for the probe filter is nice. The
same parts can be used for the consumer market with the probe filter disabled.


Regards, Hans.