Nehalem handles -120C no problems

source > Nordic Hardware
http://www.nordichardware.com/news,8057.html

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Our source installed a Core i7 processor in ASUS P6T Deluxe and threw liquid nitrogen at it, and the first tests have shown that the processor can handle temperatures as low as -120°C with ease. No coldbugs have been experienced, but we should say that it haven't tried lower than -120°C so far. Something that may very well happen within the near future.

This bodes well for the extreme overclockers that are sitting around waiting for the Nehalem architecture and even if we have no detailed performance data or even clock frequencies to share, Intel's new architecture is not far behind Yorkfield in regards to overclocked frequencies. That's as much as we could get for now, but we will keep digging!

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http://img244.imageshack.us/img244/5130/image4zm8.jpg

http://img393.imageshack.us/img393/6184/image3ee8.jpg

Promising news

But I'm itching to hear some tidibits on overclocking numbers & headroom. I thought they would have leaked by now, a few months away from launch.

Well atleast we don't have to worry about the chip coldbugging like AMD. So... now this begs the question, has it always been SOI that's caused terrible CB with AMD?

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Originally Posted by [XC] gomeler

Well atleast we don't have to worry about the chip coldbugging like AMD. So... now this begs the question, has it always been SOI that's caused terrible CB with AMD?

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The answer is yes. And Nehalem or any other bulk chip will also cold bug, just the critical temperature is much much lower.

jack

Sexy!

Now I am waiting to watch you guys, (you know who you are!) OC the hell out of this thing.

I first read it as Nehalem handles 120C no problem. I wish they could take that kind of heat!

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Originally Posted by JumpingJack

The answer is yes. And Nehalem or any other bulk chip will also cold bug, just the critical temperature is much much lower.

jack

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Do you know the technical reason for the "cold bug"? Is it because the analog portions of the chip fail? I've done VLSI/digital circuit design/device physics so please lay it on me :)

lol Asus HQ :p maybe Nehalem has the same issue as AMD that when you cool it you loose "FSB" potential, this is great news but not all is clear

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Originally Posted by Shadowmage

Do you know the technical reason for the "cold bug"? Is it because the analog portions of the chip fail? I've done VLSI/digital circuit design/device physics so please lay it on me :)

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I have read several papers on the effects of CMOS device physics with temperature both bulk and SOI. There are two potential models that make good sense to me .. both bulk and CMOS suffer from the same thing, but SOI exacerbates it... but it is important to note, i have never read any study that specifically addresses why SOI chips (CPUs) cold bug at relatively high temperatures. I only know models of temperature effects in the parametric response of SOI transistors.... it would seem that the academic journals are not populated by researchers interested in figuring out why overclockers have hard time a LN2 temps :)

1. Carrier Freeze Out -- this is difficult to explain in a short post. Essentially, the property of silicon is that electrons fall within an energy space of a band of energy levels. As every electron is in it's ground state, no current flows... for current to flow electrons must be excited into higher energy states, or a conduction band. Si is unique (as are a few other materials) because the conduction band and valence band are separated in energy, by a band gap .. where energetically electrons cannot reside.

Transistors and general MOS devices rely on this property and the ability to carefully place unique energy states in the band gap with impurities, this is called doping. By doping different regions of Si one can fashion a switch or transistor. However, to get electricity to flow the doping allows some electrons to hop into the conduction band naturally due to thermal energy (there is always some concentration electrons in the conduction band at temperatures above 0 K, and changes with temperature according to the Fermi-Dirac distribution). Carrier freeze out occurs if the temperature falls low enough that the concentration of electrons naturally populating the excited states lose that thermal energy and 'freeze' out into the ground state.

In CMOS devices, this is a function of the concentration of dopants as well, i.e. the point of freezing out significant amounts of charge carriers will vary depending on the concentration of impurities that are altering the electronic character of the material. I have seen carrier freeze out be blamed on the 'kink' effect in SOI, and this could be a culprit.

2. The second one is related to hot carrier injection (sound sexual, but I assure you, it is a well known phenomena of physics inside a transistor --- google it if you want). What happens here is that as temperature decreases, mobility of the electrons increases. What this means is that the resistance between source and drain decreases. Under a potential field, lower resistance electrons can pick up more and more kinetic energy. As they do, the chances that they will scatter randomly and a long way increases within the lattice.

As such, some electrons will scatter and, for lack of a better word, 'bury' into the oxide and become trapped, i.e. injected. This causes the oxide to charge significant, and with high enough charge can block the flow of electrons. I have seen this termed the Coulomb Blockade in various literature.

This phenomena can happen in either SOI or bulk devices, but the amount of oxide surrounding the transistor body is much less in bulk (i.e. bulk is isolated by a reversed bias PN junction, if an electron injects into this junction it simply can be grounded away on the other side). Anyway, the buried oxide of SOI can amplify this effect. So I have seen this also blamed on the 'kink' effect in SOI which could also explain why SOI devices shut down under cold temperatures.

EDIT: Here is one that discusses a very low very low cryogenic effect on SOI, it is subscription but you can read the abstract and get a sense. Here they refer to a avalanche cascade (this is different from a Coulomb Blockade) but essentially this concept is that electrons pick up enough momentum to knock core electrons out and generate a 'flood' of electrons, an avalanche. http://ieeexplore.ieee.org/Xplore/lo...653.pdf?temp=x



Jack

Damn, thanks for the break down.

Fixing it is the next step, cold bugging is not fun.

Any way for intel to examine chips for this charecteristic?

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Originally Posted by JumpingJack

2. The second one is related to hot carrier injection (sound sexual, but I assure you, it is a well known phenomena of physics inside a transistor --- google it if you want).
Jack

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hehehe good post i'm sure you arouse a lot of our younger members with such terms........there should be a disclaimer "use with caution" after your main post :D:clap::clap::ROTF:

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Originally Posted by FUGGER

Damn, thanks for the break down.

Fixing it is the next step, cold bugging is not fun.

Any way for intel to examine chips for this charecteristic?

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I am not sure there is a way around it, since it is part of the fundamental way chips are fabbed. I am sure the process could be tweaked, though from Intel's standpoint they will tweak it for nominal temperature guidelines and not cryogenic ones.

JumpingJack, its not often I see semiconductor theory outside of work, its kind of refreshing (even if my application is quite different). A mention of Fowler/Nordheim Tunneling and I would have been all yours.

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Damn, thanks for the break down.

Fixing it is the next step, cold bugging is not fun.

Any way for intel to examine chips for this charecteristic?

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I don't know.... I would suspect both AMD and Intel examine this extreme in certain circumstances. Ultra low temperature operation (or even extreme condition--temperature high and low) is important for some very specific applications -- i.e. NASA :) ... could you imagine having a chip bug out on you while orbiting the earth or on your way to Mars (i.e. rover :) ). In fact, if anyone gets to a library and does a lit search on this topic, most of the super cryogenic studies on CMOS devices are sponsored (funded) by NASA ... makes sense. How many deep space chips Intel or AMD supply is a good question, hardly any I suspect -- NASA probably has them special made with special purpose.

A google turns up some info: http://findarticles.com/p/articles/m..._8/ai_53366850
http://cosmiclog.msnbc.msn.com/archi...14/226502.aspx

If they do use either chip -- I can make a good argument why AMD would be preferred because SOI is less prone to soft errors from cosmic radiation, I can also understand good arguments why Intel would be preferred because of processing that can be more easily tailored for the cryogenic argument. However, I suspect that they would prefer much older technology (i.e. the larger litho nodes) since those would likely be more robust to the extremes of space.

Someone out there probably knows more reasons and why than I do :) ...

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Originally Posted by ether.real

A mention of Fowler/Nordheim Tunneling and I would have been all yours.

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here we go
first arousal.....but this was industry related :rofl:

i have absolutely no idea what that means but i guess google is a few clicks away

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Originally Posted by ether.real

JumpingJack, its not often I see semiconductor theory outside of work, its kind of refreshing (even if my application is quite different). A mention of Fowler/Nordheim Tunneling and I would have been all yours.

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:) My favorite topic ... I did my dissertation on similar stuff (not FNT, but just regular old Si) ... the advantage of having a degree in physics -- I understand all the gobbeldeee gooop you find in the IEEE journals ....

FNT is not quite as critical for a generation or two now that the industry appears poised to switch away from SiO2 ...

EDIT: Hang tight, I will pull up an STM image of one of my Si(100) surfaces and really get you jazzed .... I own the copyright so I can post it :) .... and if you really want to get me going, just mention Schrodinger's cat. ;)

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Originally Posted by JumpingJack

:) My favorite topic ... I did my dissertation on similar stuff (not FNT, but just regular old Si) ... the advantage of having a degree in physics -- I understand all the gobbeldeee gooop you find in the IEEE journals ....

FNT is not quite as critical for a generation or two now that the industry appears poised to switch away from SiO2 ...

EDIT: Hang tight, I will pull up an STM image of one of my Si(100) surfaces and really get you jazzed .... I own the copyright so I can post it :) ....

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Sweet!!:up:

Cant wait to google it so I can pretend like I know what your talking about.

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Originally Posted by G0ldBr1ck

Sweet!!:up:

Cant wait to google it so I can pretend like I know what your talking about.

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You can get a better idea of tunneling but just googling Quantum Mechanical Tunneling.

It is a fascinating topic really. The concept is exactly the same reason why a scanning tunneling microscope (STM) works they way it does ... an IBM invention by the way.

The concept is that electrons in two different conductors but separated spatially (i.e. not in contact) will not flow between the two conductors because of an energy barrier. However, if you can get them close enough, without touching and put a small potential difference between the two then quantum mechanics predicts that there is a measurable and finite probability that electrons in one conductor will magically disappear from one and appear inside the other ... i.e. it 'tunneled' through the barrier without being in contact.

This is, in fact, the major source of leakage since 130 nm technology, and the reason for the push to non-SiO2 gate oxide materials.

It is also the phenomena that prompted my reference to Schrodinger's Cat above ... if you are a true geek and want to read more of a generalized 'layman's' book on the philosophy, read In Search of Schrodinger's Cat by Gibbens (I think it is Gibbens, not sure).


Jack

Damn. This all make me want to go back and get my BAS in EE.

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Originally Posted by JumpingJack

The answer is yes. And Nehalem or any other bulk chip will also cold bug, just the critical temperature is much much lower.

jack

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Would it be safe to assume that some of these may be more prone to coldbug than others, like how some AMD CPUs had no issues at -80C while others wouldn't tolerate even 0C?

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Originally Posted by SparkyJJO

Would it be safe to assume that some of these may be more prone to coldbug than others, like how some AMD CPUs had no issues at -80C while others wouldn't tolerate even 0C?

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This is a good question ... I think it would, there are a few other temperature related effects on the device physics that may play a role as well ... though, those don't make as much sense to me -- they typically are at extremely low (30 K or so) where they are observed.

The carrier freeze out explanation I gave above would make the most sense I suppose since random variation or changes in different steppings could change the electrical doping levels and really jack around the critical temperature...

to be frank though, I would not even venture a guess as to why or what may cause the variability into why we see it on some CPUs and not as much as others.

I think those variations are the same reason we see 'overclockablility' changes across lots and such. Just manufacturing differences.

A little googlin' goes a long way ... found this to demonstrate what I was trying to say above:

http://extenv.jpl.nasa.gov/presentat...emperature.pdf (notice NASA :) )

See slide related to impurity freeze out....

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Originally Posted by G0ldBr1ck

Sweet!!:up:

Cant wait to google it so I can pretend like I know what your talking about.

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:rofl::D i feel you:cord:

so, how does it clock?

to those who are NDAed... 6GHz???

I´ll be waiting for some real LN2 action :D

I wonder who was the source, Asus, Sweden, LN2...:rofl: