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This sounds very interesting.
I know you didn't want to talk about it, but did you measure the resistance between VCCPLL and VSSA on a E4x00 in comparison to the higher E6xx0 Core2 Duo Models? Perhaps they didn't even change filters, but added resistance from VCCPLL to VSS in order lower the voltage, i.e. crippling the max possible FSB that way. Just a thought. I'm sorry if you already did that measurement.
It just occured to me right after having read your posting. BTW, my XEON 3050 ES is measuring 1.134K Ohm from VCCPLL to VSSA. ;)
And yes, I fully agree, or let's better say, I also assume that the modification must be on the package and not the die itself. IMHO, wouldn't make any sense considering the production process.
Unfortunately I cannot help you with your question about the P5K. I never owned one, thus I could only guess.
I did measure between VCCPLL and VSSA. Just looked it up. Had thought the processor land would be VSS, but it was VSSA indeed. Although it made no difference at all. The same 1.134k on VSS, too.
I'm not sure either if it can really be measured that way. :shrug:
As we have no exact information we will most likely be guessing to a certain degree anyway.
Perhaps some more poeple could do some measurements. Then we would see quite fast if there is a trend or if it's just a random difference.
Yes, be sure to keep up the good work. I'd really like to be more helpful, but unfortunately I doubt that I can be.
Just one more rrandom thought: If they intended to increase the noise on the analogue voltages to hamper the FSB clocking, then wouldn't it be possible that they didn't really isolate VSSA from VSS? Still just guessing.
Now that sounds good. ;) And concerning the "sabotage" part: I think we both mean to say the same thing. It's just a bit more difficult for me to express as english is not my mother-tongue. IMHO, it is sabotage in a certain way. I mean they really wanted it not to be capable of high FSB clocks, but it's not done the dirty way that sabotage usually looks like, but the sophisticated, professional, engineering way.
How about an angle-grinder? Or do you intend to still use the CPU after the modification? :DQuote:
Originally Posted by SoddemFX
subscribed
VccPLL to Vssa/Vss - 60kohms
[img=http://img231.imageshack.us/img231/5237/img1910asj0.jpg]
[img=http://img235.imageshack.us/img235/7445/img1912aqx3.jpg]
And i dont think its the noise to be blame for.
Ive isolated/separated the VccPLL from the Southbridge voltage on my DFI 965P-S and after feeding the VccPLL with a personal excellent noise filtered "maximizer" (built on a lm317a ),all i have got were just 15Mhz on BUS over my fsb wall. But just was the couse of extra voltage(like 1.95v vs. 1.8v max default)
like most of the 965 mobos,Yes.
Exactly what i have done.
Now the PLL mod is off since im playing with another board,but ill put it back monday evening and get back with some pictures.
Honestly,my hopes were greater than 15mhz up over normal fsb wall. Even with cpu on -135C i couldnt pass 590 bus on modded DFI P965 ,though my P5K Vanilla,identical test/hardware condition goes for 620.
Ill try to make a compare very soon,checking for signal clarity of VccPLL with my mod on/off over the DFI P965-S. Got an osciloscope from a friend and maybe this will make things more visible :)
WOW! I cant wait to see you results Tom! :D
Incidentally what multi are you running with at 360MHz FSB?
The SMD caps I was looking at for you were the X7R ones, but most of the companies I tried wanted a trade customer buying 1000's not me buying 50 or so lol!
Just had search at RS components and they do SMT X7R's if they are the right ones and they sell them in batches of 10 :D
Hope this is of some use.
Subscribed, interesting thread
DFI 965-s PLL Mod
Somehow kinda useless as you need an external linear supply (1.5v ->3v).
Anyway,here is it:
http://img81.imageshack.us/img81/630...5pllmodbw8.jpg
http://img81.imageshack.us/img81/717...odlargenz4.jpg
my E6700
before: fsb wall (@1.80v-SB1.5v) at 545,aircooling
after the mod: fsb wall (@2.15v PLL) at 561, aircooling
osciloscope tests for signal quality soon
also,if anyone interested for Vcore on DFI P965-s/non S, just say ..
any news?
Looking forward to how this progresses
Just out of curiosity i've noticed some "empty" pads on the bottom of many cpu's which appear to be debugging pads and etc, could be possible that putting power or grounding these might open or close off features maybe, no?
Nice! Best of luck from me! Hope the CPU still works.
I would try it in the Assrock first just to make sure it works before risking the P5K dude! :'(
got an e4300 and asrock board here but the board is limited to 300fsb absolute maximum.. :(
Better not doing that ;) these are not (as I understood you) debugging pads, but the voltage pads. Some are Vcc, some Vss or whatever. If you put power on a power rail it can make some smoke :)
The debugging is in JTAG interface, and the pads are in the LGA775. Some of the empty pads can be reserved for caps, but not used (that what this thread os about, as I read).
Can you make a foto of them?
http://www.xtremesystems.org/forums/...7&postcount=15
The smaller dots (and one square) around the inside of the square left in the center of the LGA pads in that pic
Better check the resistance to Vss and Vcc on these. Maybe it's just and outpit of them. Because they do not look like pads.
We were thinking of the FSB wall problem on ROM.by. But the only two ideas are modification of voltages (Vcca and et cetera) and the filter on the bottom. I think, a comparision of the Celeron 4xx, E21xx, E4000, E6000 and Quad should be made to see differences.