informal
Xtreme Cruncher

I'm glad you can appreciate my Turkish Spock avatar now. Turkish Spock is my hero.

I got this late but thanks alot! Yeah Sandy was never supposed to get FMA, the tock was

looking good, won't be long now....

FMA addition is really the major one.Now they extended it with 256bit vectors and it's like icing on the cake

Nice scoop on the SSE5 extensions, although it was gonna pwn with FMA already

http://xbitlabs.com/news/cpu/display...rocessors.html

12 core CPU in hand for socket G34 already.
I sense a disturbance in the force

now how do I do that little light saber fight ? lol

Yeah interesting indeed.More info here :
http://aceshardware.freeforums.org/i...-75.html#10665

(from the above post onwards the topic becomes bulldozer design).

That is intersting stuff right there. I hope the new launch date hold true, be nice to see what these do.

and like the ninja you are you pull this, I was going to make a bulldozer speculations/rumor thread.

BD cores(bulldozer) will be extremely different beasts than any Kx we have known. For a possible look about what BD could be,you can look here :
http://citavia.blog.de/ (a blog by ace's hw member known as dresdenboy).

Quote from the article:" It's time for my first blog post after publishing my thoughts in several forums for years.

I want to start with a graphic (first published on planet3dnow) showing what some of AMD's last year's patent applications contained as an exemplary MPU architecture. It's worth to note, that this architecture fits nicely to some rumor brought up by Charlie on the Inquirer.

Another hint is this old AMD presentation, which mentions future developments like "Throughput Architecture" and "Cluster-based Multi-threading", although not explicitly stating its planned use. However, both sources tell us about some clusters. Now this is, what appeared in the patent applications:

Additionally there are many other interesting bits hidden in many different patent applications (long numbers) and filed patents (shorter numbers):

* clustered multithreading with 2 int clusters with each of them having:
o 2 ALUs, 2 AGUs
o one L1 data cache
o scheduler, integer register file (IRF), ROB
(see 20080263373*, 20080209173, 7315935)
* a trace cache, not to make cheaper decoders but to quickly recover from a mispredicted branch (7197630 and many others)
* read port arbitration for a faster IRF (7315935)
* shared FPU supporting ADD, MUL, FMAC etc. and 64 or 128 bit max. operand width (20080263373)
* FPU may run in full bit or reduced bit modes to save power (20080209185)
* 32 byte fetch, 4-way Decoder - multithreaded round robin or depending on queue saturation (20080263373, EP1244962)
* fine grained power management (token based, 20080263373) for optimal usage of given TDP/ACP
* a lot more speculation (data speculation, cache way prediction, see 7024537, 7028166 and many others)
* 2 loads from L1 D$ per cycle per cluster (7502914)
* maybe 2 cycle effective L1 D$ latency instead of 4 thanks to replaying (7502914)
* possibly a shared L2 (7502914)
* loop detectors (7130991)
* dynamically scalable cache architecture to save power by switching off cache portions or levels (20080104324)
* AMD's turbo mode (running cores faster if others are less utilized, 7490254, filed 2005/08/02)

Even if only some of these points will be true for Bulldozer, it will be a very interesting MPU."

Basically if above has any ground in reality,BD cores will be multithreading beasts.