K8L photo?

[IvanAndreevich]

http://tweakers.net/nieuws/41908/AMD-toont-45nm-wafer-levert-eerste-90nm-chips-uit-Fab-36.html

I think it might be. Certainly looks interesting.

[nn_step]

looks like mixed L2
http://img.photobucket.com/albums/v643/nn_step2/1144182684.jpg
or just 4Mb of L3

[Thorry]

Well that's not L3 for sure.

You can clearly see the L1 cache block on the left (above the big cache block) and the data cache block on the right (above the big cache block).

If this were L3 where then is the L2, make no mistake this is regular L2.

When this would be a 100% die shrink from 90nm the size relation between the core and the amount of cache is equal, the blocks in the middle are also present in all previous cache designs so that's nothing new there. I would say this is 1MB of L2 cache, just plain old L2. If the circuits run underneath the purple part it can be 2MB, but can't say from this picture.

Also this is a single core, prolly a Turion test chip since there will most likely only be dual and quad core 65nm desktop chips from AMD.

If you examine all parts, memory controller, Instruction fetch, EXU, BU, FPU, Load store units etc. you will clearly see this is 100% die shrink of 90nm single core DDR2. You can clearly make out the DDR2 memory controller and the FPU, they are the same also the instruction fetch is 100% the same. The EXU and BU are a bit harder to make out but I see no real differences there so it's clearly a simple die shrink, no big whoop.

If it weren't for the text printed on the picture you wouldn't even know it's 65 nm

Here I've drawn in the different blocks inside the CPU:
http://www.thorry.net/cpu_explained.jpg

I recognize all the parts and see nothing new in this.

[nn_step]

notice the Purple part near the bottom of the Chip
that is not Regular L2 and you know it...

[Thorry]

I don't know what the purple part is, it could be drawn in, or be filled with test circuits.

It could also be left blank, that this is the 1 MB part and the 2MB part has the purple bit filled with L2 memory circuits.

There is no circuit that would create such a purple color and show no lines whatsover, it's either blank or filled with test patterns (very small with no function but to check the wafer).

If it were circuits you would see blocks, paths and interface parts, here there is nothing...

If you check at the top of the memory controllers you see some purple there (but it shows as a different purple, more pink like). That's insulation for the clock generators located there (3 of them clearly visible), there is no circuit on that purple bit so I don't think the bottom purple bit has any circuits, or has something we aren't supposed to see.

If you send a mail to Wouter Tinus over at Tweakers.net you will get the answer, he is the local CPU expert and the poster of both the article and the picture. His e-mail address: Wouter@Tweakers.net

[eBoy0]

I don't know what the purple part is, it could be drawn in, or be filled with test circuits.

It could also be left blank, that this is the 1 MB part and the 2MB part has the purple bit filled with L2 memory circuits.

There is no circuit that would create such a purple color and show no lines whatsover, it's either blank or filled with test patterns (very small with no function but to check the wafer).

If it were circuits you would see blocks, paths and interface parts, here there is nothing...

It clearly looks like it was drawn in to hide whatever is behind it.

[Thorry]

Yeah looks drawn in, I concur with that, also the placing of the text is very 'handy'.

However what could be there we aren't supposed to see?

L2 cache is the most basic memory you can get, at 65nm in this picture you are seeing about 1MB of L2 cache. If there were other cache circuits behind the purple bit there could only be about 1MB of any kind of cache behind that.

It's way to far away from the rest of the core to be any kind of logical circuit so it has to be memory.

My conclusion: There is nothing there, even with the smallest memory available there is only room for 1MB. 1MB of L3 cache doesn't make sense. Also Z-RAM (the technique AMD has slated to use in 2007 and 2008) is bigger (more circuits needed for the same size memoryblock) so there would be less then 1MB...

The way it's been cut off also seems strange, if there was any kind of different circuit there would be some room between those, but the purple is right up against it. It's prolly just drawn in over more L2 cache, giving the 2MB L2 cache I drew in the picture.

[nn_step]

Yeah looks drawn in, I concur with that, also the placing of the text is very 'handy'.

However what could be there we aren't supposed to see?

L2 cache is the most basic memory you can get, at 65nm in this picture you are seeing about 1MB of L2 cache. If there were other cache circuits behind the purple bit there could only be about 1MB of any kind of cache behind that.

It's way to far away from the rest of the core to be any kind of logical circuit so it has to be memory.

My conclusion: There is nothing there, even with the smallest memory available there is only room for 1MB. 1MB of L3 cache doesn't make sense. Also Z-RAM (the technique AMD has slated to use in 2007 and 2008) is bigger (more circuits needed for the same size memoryblock) so there would be less then 1MB...

The way it's been cut off also seems strange, if there was any kind of different circuit there would be some room between those, but the purple is right up against it. It's prolly just drawn in over more L2 cache, giving the 2MB L2 cache I drew in the picture.
actually Z-Ram takes up 1/6th the space of normal cache.. hence I said it could also be 4Mb of L3

[dinos22]

s7 said L3 cache is coming...that's what the drawn bit must be donno

[Thorry]

I mailed Wouter Tinus, perhaps he can give the answer.

nn_step: You should know damn well by now you shouldn't make such statements without any explaination or source.

Z-ram is stated to be potentially 5 times denser, this doesn't mean it will be smaller on the die.
This will also not mean there aren't any blocks. Also the interface blocks would be the same as for the L2 cache.

If you check out this graph:

http://www.digitimes.com/NewsShow/20060328PR202_files/image010.jpg

You will see the density difference between Z-ram and SRAM is about 3, so there isn't enough room for a lot of L3 cache if that is what the space is for / covered up. Also the interface circuits would be the same size so the blocks would be equal size for the SRAM as for the Z-RAM. However the blocks would contain more data for Z-RAM as for SRAM, but you can't see that on such a photo.

[nn_step]

you are right and initially it is only half the size
http://www.us.design-reuse.com/news/news9538.html

[Shadowmage]

This may help explain it :)

http://www.aceshardware.com/forums/read_post.jsp?id=115160463&forumid=1

More pics:

90nm and 65nm side-by-side: http://139.30.40.11/K8_compare_90_65nm.jpg

EDIT:

Even more pics:

HUGE 65nm shot: http://crew.tweakers.net/Wouter/AMD65nm.jpg


EDIT2:

Hans speaks!



Name: Hans de Vries (hansdevries@chip-architect.com) 4/6/06

ten9 (jhdjksa@huhu.com) on 4/6/06 wrote:
---------------------------
>Hello Hans,
>
>Do you think there is a fourth decoder like Gipsel argues
>here:
>
>http://www.aceshardware.com/forums/read_post.jsp?id=115160237&forumid=1
>


These are the micro-code ep(roms) for complex cisc
instructions. They operate as one single memory since
they all get the same address from the micro-sequencer
which handles the complex instructions. Going from 3 to
4 therefor doesn't say anything at all, it's just more
memory, or the same amount of memory with larger cells.
The rest of the architecture is visibly 3-way. The re-
order buffer, the integer schedulers, the integer ALU's.


>And what do you think about the floating point units?
>


It's virtualy identical to existing K8's. There are also 3 HT
units and not 4 as claimed by somebody at aces. It's not a K8L.


>Regards,
>
>Ten9
>


It seems to be an earlier prototype in which they were still
experimenting with the new much denser L2 cache. The fact
that they left open such a wide area with the size of the
old cache means they were not sure enough about it at that
time. Showing the cache now would imply that it must be OK.

More cache would be the most important thing for AMD to
counter Conroe's integer IPC.


Regards, Hans

[Cybercat]

So if there's no change to the logic circuits, and it's just a die shrink, it can't be the K8L then?

[Shadowmage]

It's not K8L

Anyways, Brett Vankirk and I did a rough calculation of transistor count for Conroe, and we got ~200mil for the logic + L1 only, no L2. Compare that to ~45.6mil of AMD (again, very rough estimate).

[MaxxxRacer]

200mil for logic on Conroe.. thats just nutty.. estimate or not it seems a WEE bit high.

anyone else notice the VERY large sections of the core dedicated to memory and HTT interface. much more so than the current K8's.

[Cobalt]

I never thought it was the K8L fro the moment I looked at it. Its too early for us to be seeing anything like this and my first though was that its just a test die for the 65nm shrink or a new cache technology. Looks like I was probably right. (go me:woot:)

[jrw]

PCI-E controller on die?

[krille]

in wich way could adding L3 bring advantage?As with all cache and memory, it lowers memory latencies on certain cache misses (ie Level 2 miss but Level 3 hit). Less clock cycles wasted waiting for data. Basically reduces performance hit on cache misses.

[craig588]

Yes.

[nn_step]

200mil for logic on Conroe.. thats just nutty.. estimate or not it seems a WEE bit high.

anyone else notice the VERY large sections of the core dedicated to memory and HTT interface. much more so than the current K8's.
That is mostly do a improvements to the 65nm core

[Shadowmage]

Yeah, it probably is high... guessing die size sucks :(

Probably more like 150mil-ish

[nn_step]

Yeah, it probably is high... guessing die size sucks :(

Probably more like 150mil-ish
That is a 50% boost in Transistor count man..

[Thorry]

Well that there were 3 HT interfaces I could see even on the low-res pic.

This confimes it then: It's just a die shrink of the current 90nm, they are using a bit more dense cache but didn't know how much space to allocate. There's prolly between 1MB and 2MB on this part, the final product may have 2 or 4MB depending on how yields turn out.

The purple space is simply clear space reserved for cache memory...

(Haven't heared from Wouter yet, he may have some insights)