A64 dual core 2,5sec better Superpi 1M!!!

[misteroadster]

I was reading the HKEPC test of opteron 866 when i've discovered that, Very good news !!!

http://www.overclocking-masters.com/forum/viewtopic.php?pid=7523#p7523

[mrlobber]

Wow, I just discovered I can read French :D

... or is it all overclockers speak one language deep inside? :toast:

[ozzimark]

i was under the impression that a shared cache wouldn't happen until 65nm with an L3 between the two?

[Eversor]

I was reading the HKEPC test of opteron 866 when i've discovered that, Very good news !!!

Finally HTT is not so useless :banana:

http://www.overclocking-masters.com/forum/viewtopic.php?pid=7523#p7523

at least from what amd states in their documents, the cache IS NOT shared.

The improvement may come from improvements done to the core, and the SSE3, wich can be used if the super pi is patched to it.

Even if the cache is shared, that would be great for single-threaded applications, but not for multi-threaded. Maybe AMD64 dual-core may have shared cache, opteron not, since it's main use will be multi-threading.

[Pjotr]

i was under the impression that a shared cache wouldn't happen until 65nm with an L3 between the two?

It has two separate L2 caches, one per core.

[drunkenmaster]

posted this link in overclocking forum, cos most people look there http://www.hexus.co.uk/ some info on the dual core names, speeds on front page, more to follow.

I mean the server ones got bumped forward from q3(late q3 i think) to this month, no reason they can't do the same for desktop, they are the same chips just diff numbers on the front. in which case intel should be crying themselves to sleep tonight. :p

[ozzimark]

at least from what amd states in their documents, the cache IS NOT shared.

The improvement may come from improvements done to the core, and the SSE3, wich can be used if the super pi is patched to it.

Even if the cache is shared, that would be great for single-threaded applications, but not for multi-threaded. Maybe AMD64 dual-core may have shared cache, opteron not, since it's main use will be multi-threading.
i don't think amd will change the opteron dual core much to fit into the a64-X2 clothing... probably just drop the extra pin to make it 939.
thanks for comfirming my thought on shared cache though :D

[misteroadster]

how do you explain the 2.5 sec gain otherwise ?

[Minstadave]

SSE3, tweaked architecture, better memory controller?

AMD dual core architecture involves individual L2 caches AFAIK.

[misteroadster]

I think the hkepc tester has done those benchmark in equal condition for both CPU.
We can see the same improvement (just a little less coz better latency beetween dual core) with the biopteron 248 (C0).
I think the processors communicate on the HTT bus even in monothread applications.
Really strange, nobody noted that before.

And what do you think about those results with SLI (6800U stock) and biopteron :
http://www.nvnews.net/vbulletin/showthread.php?t=45964

Really really really strange, no ???

[saaya]

whats so strange about those results?

so is the cache shared or not? hmmmm

[misteroadster]

3D Mark 05 1024x768 11,113

3D Mark 03 1024x768 25,281

those score are impressive for stock 6800U or i'm mad ?????

i think L2 are shared even with Biopteron.
Really hard to affirm that, i never touched any multi K8 setup :mad:
But those results are really strange for me.

[saratoga]

I think the hkepc tester has done those benchmark in equal condition for both CPU.
We can see the same improvement (just a little less coz better latency beetween dual core) with the biopteron 248 (C0).
I think the processors communicate on the HTT bus even in monothread applications.
Really strange, nobody noted that before.

And what do you think about those results with SLI (6800U stock) and biopteron :
http://www.nvnews.net/vbulletin/showthread.php?t=45964

Really really really strange, no ???

It doesn't use HT for intercore communication. Thats what the SRQ is for. And why AMD explained this years ago.


i think L2 are shared even with Biopteron.
Really hard to affirm that, i never touched any multi K8 setup
But those results are really strange for me.

AMD literally explained this all 3 or 4 years ago. Its not like its hard to google things. Theres no shared L2. At all. Its just two cores connected to the HT and memory via SRQ. Same as single core 64s, except now theres two cores on the SRQ instead of one.

[misteroadster]

ok, so those results are inexplainable :/

[terrace215]

ok, so those results are inexplainable :/

No, they have already been explained to you:

- Dual CG single cores vs. single Rev E dual core

- With a single Rev E dual core, all memory is local. With 2 single cores, there is local and remote memory.

[misteroadster]

ok , for you it's normal 2sec better at superpi 1M and 9 sec at superpi 4M between 1X248 Opteron and 2X248 ?
Not for me sorry.

take a look here : http://www.hkepc.com/hwdb/dualcore-opteron-5.htm

But there is no gain between 1X866 and 2X866 :mad:

[terrace215]

ok , for you it's normal 2sec better at superpi 1M and 9 sec at superpi 4M between 1X248 Opteron and 2X248 ?
Not for me sorry.

take a look here : http://www.hkepc.com/hwdb/dualcore-opteron-5.htm

But there is no gain between 1X866 and 2X866 :mad:


It is normal because the 2nd core can handle the background OS tasks that otherwise slow down the superpi run.

As far as gains from 1x866 to 2x866, well, if you run single threaded benchmarks, you aren't going to see many gains, now are you?

That said, look, this review is not top quality. Just wait for next Thursday, and there will be a lot more information.

[saaya]

thx a lot terrace! :toast:

[misteroadster]

yes you're probably right terrace.
so 2 sec at 1M would be a good improvement, i want to see a P4 DC benching Superpi.
Thanks for the modification of the thread title :toast:

[pirox]

It's faster because both cores have access to both caches. So what does this mean? In a single threaded app, 1 core has access to 2MB of cache. That is...if both cores have 1 MB of cache at least. Now we come back to why Dothan is so good @ super PI. it's not because it does more per clock...but it's because SUPER PI runs in it's caches as well as some other app's around that. The dothan in itself is therefore not capable @ the moment to produce enough IPC out of it's units to match a P4 or A64. And as you know a dothan has 2 MB of very low latency l2 cache. Having more cache also means that a CPU does not need to fetch too much data from memory. Take a look @ Banias...it only had 1 MB of cache. it performed really badly....

So as such an A64 that has as much cache as a Dothan will definately score better @ synthetic benches as SUPER PI. Combine that with a low latency mem controller if mem access ever occurs and you'll have a beast.

[EMC2]

And here's an official released AMD die plot showing the two individual caches for the two cores ;)

http://www.amd.com/us-en/assets/content_type/DigitalMedia/dualcore_hires.jpeg

For comparison, here's a marked up A64 single core:

http://www.amd.com/us-en/assets/content_type/DigitalMedia/Ath64_die_marked_E.jpg

[M.Beier]

.... Holy crap thats a pricy system...

Dual opteron
16GB mem..
1,6TB HDD.....

GaaaH