Xtreme Terminology

[Waxman]

This thread is for all the newbies that join to XS to learn a little bit more about computers and how to overclock them.

All the terminology used here at XS related to overclocking will be explained here on this thread.

I'll start with the basics and I ask to all of the members of XS to help me complete this task so that the newbies can understand what the hell we are talking about. :D

Here we go:

Motherboard related

AGP - Accelerated Graphics Port, an interface specification developed by Intel Corporation. AGP is based on PCI, but is designed especially for the throughput demands of 3-D graphics. Rather than using the PCI bus for graphics data, AGP introduces a dedicated point-to-point channel so that the graphics controller can directly access main memory. The AGP channel is 32 bits wide and runs at 66 MHz. This translates into a total bandwidth of 266 MBps, as opposed to the PCI bandwidth of 133 MBps. AGP also supports two optional faster modes, with throughputs of 533 MBps and 1.07 GBps. In addition, AGP allows 3-D textures to be stored in main memory rather than video memory.
AGP has a couple important system requirements:

The chipset must support AGP.
The motherboard must be equipped with an AGP bus slot or must have an integrated AGP graphics system.
The operating system must be the OSR 2.1 version of Windows 95, Windows 98 or Windows NT 4.0. And currently, many professional Macintoshes support AGP.
AGP-enabled computers and graphics accelerators hit the market in August, 1997. However, there are several different levels of AGP compliance. The following features are considered optional:

Texturing: Also called Direct Memory Execute mode, allows textures to be stored in main memory.
Throughput: Various levels of throughput are offered: 1X is 266 MBps, 2X is 533 MBps; and 4X provides 1.07 GBps.
Sideband Addressing: Speeds up data transfers by sending command instructions in a separate, parallel channel.
Pipelining: Enables the graphics card to send several instructions together instead of sending one at a time.


BIOS - Basic Input/Output System -the built-in software that determines what a computer can do without accessing programs from a disk. On PCs, the BIOS contains all the code required to control the keyboard, display screen, disk drives, serial communications, and a number of miscellaneous functions.
The BIOS is typically placed in a ROM chip that comes with the computer (it is often called a ROM BIOS). This ensures that the BIOS will always be available and will not be damaged by disk failures. It also makes it possible for a computer to boot itself. Because RAM is faster than ROM, though, many computer manufacturers design systems so that the BIOS is copied from ROM to RAM each time the computer is booted. This is known as shadowing.

Many modern PCs have a flash BIOS, which means that the BIOS has been recorded on a flash memory chip, which can be updated if necessary.

The PC BIOS is fairly standardized, so all PCs are similar at this level (although there are different BIOS versions). Additional DOS functions are usually added through software modules. This means you can upgrade to a newer version of DOS without changing the BIOS.

PC BIOSes that can handle Plug-and-Play (PnP) devices are known as PnP BIOSes, or PnP-aware BIOSes. These BIOSes are always implemented with flash memory rather than ROM.

Chipset - Motherboard's hardware controller - It controls the flow of information and data from one point to another. It can be separated in two chips (Northbrige and Southbridge) or it can be a single chip (Nvidia based chipsets NF3 and NF4)

CMOS - Complementary Metal Oxide Semiconductor - CMOS is a widely used type of semiconductor. CMOS semiconductors use both NMOS (negative polarity) and PMOS (positive polarity) circuits. Since only one of the circuit types is on at any given time, CMOS chips require less power than chips using just one type of transistor. This makes them particularly attractive for use in battery-powered devices, such as portable computers. Personal computers also contain a small amount of battery-powered CMOS memory to hold the date, time, and system setup parameters.

CPU socket - It's where you insert your cpu (It can be a ZIF (Zero Insertion Force) socket or a LGA (Land Grid Array) socket

Dimm slot - The place where the memory modules are inserted

FSB - Front side bus -The bus that connects the CPU to main memory on the motherboard. I/O buses, which connect the CPU with the systems other components, branch off of the system bus.The frontside bus is also called the system bus, memory bus, local bus, or host.

HTT - Hypertransport - Communications pathway between the cpu and the expansion slots (PCI, PCI-Express, AGP). Found only on AMD's A64 CPU based computers.

Northbrigde - The motherboard controller that acts like a brige between the CPU and the memory slots.

Southbridge - The motherboard controller that acts like a brige between the CPU and the expansion slots.

Alright, some memory related words here (thanks to moddolicious and D_o_S)

CAS Latency
The CAS latency is the delay, in clock cycles, between sending a READ command and the moment the first pice of data is available on the outputs.

tWR - Write Recovery Time:
tWR is the number of clock cycles taken between writing data and issuing the precharge command. tWR is necessary to guarantee that all data in the write buffer can be safely written to the memory core.

tRAS - Row Active Time:
tRAS is the number of clock cycles taken between a bank active command and issuing the precharge command.

tRC - Row Cycle Time:
The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC.
tRC = tRAS + tRP

tRCD - Row Address to Column Address Delay:
tRCD is the number of clock cycles taken between the issuing of the active command and the read/write command. In this time the internal row signal settles enough for the charge sensor to amplify it.

tRP - Row Precharge Time:
tRP is the number of clock cycles taken between the issuing of the precharge command and the active command. In this time the sense amps charge and the bank is activated.

tRRD - Row Active to Row Active Delay:
The minimum time interval between successive ACTIVE commands to the different banks is defined by tRRD.

tCCD - Column Address to Column Address Delay

tRD - Active to Read Delay ?:

tWTR - Internal Write to Read Command Delay:
tWTR is the delay that has to be inserted after sending the last data from a write operation to the memory and issuing a read command.

tRDA - Read Delay Adjust
(got it from here http://www.techpowerup.com/articles/overclocking/64)

update (little more info)

Max Asynce lantency= 00.0-15.0 in 1.0 incements.
I would suggest trying 5.0-10.0 depending on your ram. 5ns will problobly not allow much overclocking, and 7-8ns is usually the optimal

Read Preamble time= 02.0-09.5 nano sec, in 0.5 increments.

I would suggest 4.0-7.0 depending on ram. 4ns will probobly not allow for much overclocking, and 5-6ns is usually the optimal

[felinusz]

BIOS - Basic Input/Output System -the built-in software that determines what a computer can do without accessing programs from a disk. On PCs, the BIOS contains all the code required to control the keyboard, display screen, disk drives, serial communications, and a number of miscellaneous functions.
The BIOS is typically placed in a ROM chip that comes with the computer (it is often called a ROM BIOS). This ensures that the BIOS will always be available and will not be damaged by disk failures. It also makes it possible for a computer to boot itself. Because RAM is faster than ROM, though, many computer manufacturers design systems so that the BIOS is copied from ROM to RAM each time the computer is booted. This is known as shadowing.

AKA Built In Operating System :).

I'll delete this post if you want me to bro :)

[Waxman]

You don't need to delete it, but every online enciclopedia that I've seen says that the definition of BIOS is the one that I posted. ;)

[matt9669]

The definition for BIOS is correct, Basic Input/Output System. Thanks Waxman!

[MaxxxRacer]

That it is. Felin, where did you get that definition of it. im curious?

[matt9669]

Dimm slot - The place where the memory modules are insertedDIMM stands for Dual Inline Memory Module, as opposed to the earlier SIMM or Single Inline Memory Module which had to be inserted as pairs. :toast:


HTT - Hypertransport - Communications pathway between the cpu and the expansion slots (PCI, PCI-Express, AGP). Found only on AMD's A64 CPU based computers.Don't forget the XBox! :rofl:

[Waxman]

DIMM stands for Dual Inline Memory Module, as opposed to the earlier SIMM or Single Inline Memory Module which had to be inserted as pairs. :toast:


That will be covered on the memory section.

I didn't have the time to update the thread today because I had an express service @ work. 14 hours spent working on it and the day only has 24 hours. I'm dead tired.

[matt9669]

What? Get back to work slacker! :cord: :rofl:

LOL no worries bro, thanks for getting this started :up:

[D_o_S]

Alright, some memory related words here (thanks to moddolicious)

CAS Latency
The CAS latency is the delay, in clock cycles, between sending a READ command and the moment the first pice of data is available on the outputs.

tWR - Write Recovery Time:
tWR is the number of clock cycles taken between writing data and issuing the precharge command. tWR is necessary to guarantee that all data in the write buffer can be safely written to the memory core.

tRAS - Row Active Time:
tRAS is the number of clock cycles taken between a bank active command and issuing the precharge command.

tRC - Row Cycle Time:
The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC.
tRC = tRAS + tRP

tRCD - Row Address to Column Address Delay:
tRCD is the number of clock cycles taken between the issuing of the active command and the read/write command. In this time the internal row signal settles enough for the charge sensor to amplify it.

tRP - Row Precharge Time:
tRP is the number of clock cycles taken between the issuing of the precharge command and the active command. In this time the sense amps charge and the bank is activated.

tRRD - Row Active to Row Active Delay:
The minimum time interval between successive ACTIVE commands to the different banks is defined by tRRD.

tCCD - Column Address to Column Address Delay

tRD - Active to Read Delay ?:

tWTR - Internal Write to Read Command Delay:
tWTR is the delay that has to be inserted after sending the last data from a write operation to the memory and issuing a read command.

tRDA - Read Delay Adjust
(got it from here http://www.techpowerup.com/articles/overclocking/64)

update (little more info)

Max Asynce lantency= 00.0-15.0 in 1.0 incements.
I would suggest trying 5.0-10.0 depending on your ram. 5ns will problobly not allow much overclocking, and 7-8ns is usually the optimal

Read Preamble time= 02.0-09.5 nano sec, in 0.5 increments.

I would suggest 4.0-7.0 depending on ram. 4ns will probobly not allow for much overclocking, and 5-6ns is usually the optimal

[Waxman]

1st post updated

[Quanticles]

CMOS - Complementary Metal Oxide Semiconductor - CMOS is a widely used type of semiconductor. CMOS semiconductors use both NMOS (negative polarity) and PMOS (positive polarity) circuits. Since only one of the circuit types is on at any given time, CMOS chips require less power than chips using just one type of transistor. This makes them particularly attractive for use in battery-powered devices, such as portable computers. Personal computers also contain a small amount of battery-powered CMOS memory to hold the date, time, and system setup parameters.

Silicon is the semiconductor, CMOS just refers to the way it's used.

Both NMOS and PMOS transistors are being used at any given time, the reason CMOS uses less power is because the gate forms a capacitor (Metal - Oxide (capacitive insulator) - Semiconductor). Since no DC current can flow through a capacitor, the only power dissapation is due to the charging and discharging of the capacitors associated with the transistors.

The oxide is silicon dioxide (S02). Since silicon is the only semiconductor that easily forms an oxide, it is the only semiconductor used to for MOSFET's.

MISFET's (Metal Insulator Semiconductor Field Effect Transistor) uses the same general prinicpal, but may use a non-oxide insulator. GaAs is a popular kind. It's extremely high speed, much faster than Silicon, but also extremely expensive. Only special equipment uses this kind of MISFET.

[Quanticles]

HTT - Hypertransport - Communications pathway between the cpu and the expansion slots (PCI, PCI-Express, AGP). Found only on AMD's A64 CPU based computers.HTT stands for Hyper Transport Technology. Many people call it just HT, or HT link. It can also be used for devices other than AMD processors, you just wont find it on an Intel board. It actually is used to communicate between the processor and the chipset, or for MP opteron systems, between the different processors too.


Northbrigde - The motherboard controller that acts like a brige between the CPU and the memory slots.It also connects to the graphics card.

[Quanticles]

LDT - Lightning Data Transport
This is what HT used to be called before they thought of a better name to copyright. It's still used in BIOS.

MP - Multi-Processor

SP - Single-Processor

Multiplier - In general, a number that multiplies another (the Front Side Bus in computing). In specific, usually refering to the CPU multiplier. A FSB speed of 200 MHz and a CPU multiplier of 10 will yeild a processor speed of 2 GHz.

[craig588]

Normally when we talk about multiple procs we say SMP. When I hear MP I think multiplayer.

[Quanticles]

Normally when we talk about multiple procs we say SMP. When I hear MP I think multiplayer.

okay x.x

what's the S?

I guess you often see 2P, 4P, 8P too.

[n_u_f_a_n]

okay x.x

what's the S?

I guess you often see 2P, 4P, 8P too.

S in SMP is for symmetric as in symmetric multiprocessing

[craig588]

Even when they arn't symmetric CPUs we still use SMP to avoid confusion with MP. It's like when we use IHS to avoid confusion with HS.

I have never heard using SP to describe a single processor system. When I head SP I think single player or spelling error depending on the conext.


We could just have all of the definitions listed with a number next to each like the dictionary does.

[Quanticles]

i guess it doesnt come up that often anyway, nvm!

[perkam]

U missed one: Pwnz0rz :rofl:

NO seriously though, u have definition of AGP but where's the unabbreviated form of and info on PCI-Express ??

Perkam

[SoddemFX]

Some of the images in this are taken from other sites as i thought it pointless to re-draw them just for the sake of it. However should anyone have any objections could a mod please edit accordingly :) All sites used are referenced.

This is by no means a complete guide but i believe it to be correct and may provide some understanding.

Overview of PCIe

PCIe uses 2 LVDS (low voltage differential signaling) wire pairs working at a very high signaling rate of 2.5Gbps. Two pairs are called one "lane" and the x16 means that there are 16 lanes. Each lane can deliver around 250MB/s giving 4000MB/s for a x16 PCIe

Each PCIe lane uses two wire pairs, one for upstream and one for downstream. This makes the throughput symmetric and allows full duplex (both ways at the same time) transmission. This is unlike AGP which allows a very high downstream throughput of 2133MB/s but has a much lower upstream throughput.

Electrical Aspects

The physical communication method is Low Voltage Differential Signaling (LVDS). Differential Signaling (DS) uses a wire pair to represent logic levels as opposed to the single ended (SE) methods used by legacy hardware. The reason for using DS is that of signal integrity at very high baud rates (level changes per second).

At a very high Baud rate, our intended signal (bottom) would be transformed into the top image:

http://img76.imageshack.us/img76/4961/setrans4wj.jpg

The reasons for this are mainly capacitance between tracks (which opposes a rapid change in voltage) and slew rate (essentially how quickly the driving amplifiers can change voltage levels).

With DS this has much less impact. It doesn’t matter if the voltage levels are reduced in amplitude (within reason), as long as there is a difference for the difference amplifier to work with.

With DS the intended signal (bottom) is converted into the DS (middle) and transmitted along the wire pair into the difference amplifier at the other end (top). The difference amplifier then recovers the original signal by comparing the two voltage inputs.

http://img302.imageshack.us/img302/3048/intdsamp8dl.jpg

DS also offers and immunity to interference, which SE transmission does not. Suppose in transmission electromagnetic interference caused a large voltage spike in the DS. Because the wire pairs always run in parallel very close to each other the spike will be present in both wires. Again (within reason) the signal can be recovered.

This more advanced signaling is needed due to the very high transmission frequencies necessary in replacing a large parallel interface with a narrow serial interface for example AGP to PCIe.

To reduce inter symbol interference at the high signaling rates a method called 8B/10B is used to encode the serialized data on each lane. This represents 8-bits as 10-bits to provide a net DC ‘0v’ on the communication line.

As 10-bits are used to transmit 8-bits (1-byte) of data the 2.5GBaud provides a raw throughput of 250MBps per lane, however not all of this can be used to transmit useful data. Away from the physical side PCIe is a packet based interface, much more alike USB than it is to traditional “wide bus” PCI and AGP. The following diagram was taken from National Instruments:

http://img305.imageshack.us/img305/1866/1342e29kt.gif

And the following from www.Interfacebus.com:

http://www.interfacebus.com/Design_PCIe_Protocol_Format.gif


This means that control information in the form of headers must be transmitted at the transaction layer in addition to frame, sequencing and error checking in the 2 layers preceding. These are not set values so the throughput will depend on the commands being issued or the tasks performed.

True data efficiency probably lies in the region of 80% or so (I am guessing) which would give 200MB/s throughput per lane. If anyone has some method of checking my guess please jump in.

Beyond the layers 3 layers listed PCIe behaves like traditional PCI with regards to Windows / enumeration etc. I’m not a software guy, so if anyone has more details…

Topology of PCIe

PCIe cards are connected in such a way that each card has a point-to-point link with a switch as opposed to the bus arbitration required by PCI devices. The following diagrams have been taken from arstechnica.com

Bus arbitrations based system:

http://arstechnica.com/paedia/images/shared-bus.png

Point to point link system:

http://arstechnica.com/paedia/images/point-to-point.png

In this case the only advantage of PCIe over AGP is that of data throughput (~3200MBps vs. 2133MBps) as AGP is a point to point link anyway. If a graphics card is being used for less conventional uses (maybe video capture?) the equal downstream throughput should provide a very large advantage over AGP. For PCI devices, especially those requiring frequent bus accesses, the gains in latency will provide a great advantage.

PCIe clock frequency

This has taken me quite some time come to an explanation I am happy with and I’m still not sure it is entirely correct.

PCIe has a base frequency of 100MHz, this is fed into a clock multiplier which increases the frequency by an effective 25x using one (or possibly 2) PLL. For example if the base clock is increased to 120MHz the differential signaling rate is now 3Gbps. The line coding used (8B/10B) should allow for clock recovery, but I’m not sure if it is currently being used to do so. From a few documents I’ve read it does appear that clock recovery may be included in future PCIe implementations, if it isn’t already.

Due to the limiting factors such as line capacitance and slew rate, the only way I can see to increase the maximum PCIe frequency is to increase the voltage output of the driver IC’s, even then the de-serialiser at the other end may be/still be the limiting factor.

The following diagram was taken from a RAMBUS developers forum and shows a future (or even current?) two stage clocking system:

http://img305.imageshack.us/img305/8770/2stageclocking5ow.jpg

Also some have suggested that newer cards such as the 7800GTX somehow regulate their core frequency by using the PCIe clock as a reference with a series of in-built multipliers. I don’t know if this is true, if anyone does please add to this.

Hopefully someone may find this useful. If any mods wish to change or move this feel free to do so.

Regards,

Tom

[Lufusol]

Silicon is the semiconductor, CMOS just refers to the way it's used.

I thought CMOS = Carbon Metal Oxide Substrate, never heard "complimentary metal oxide semiconducter" before.

Slap me if I'm being a n00b. :)

[Big SturL]

I think there should be some additions to this thread. Terms like "Vdroop" and... well... something regarding overclocking and terms and definitions one might stumble upon there.

[MindhacK-]

Nice one, thanks!