PiLsY
09-30-2002, 04:37 AM
Hi guys :).
Thought id share a few thoughts on Dual DDR for the P4. Over the next month well be seeing dual ddr chipsets from Via and SiS. Theyre both schedules for a late october release, so its sooner than you think :). The Intel Granite Bay dual ddr chipset is due out late november, so a way to go for intel yet. Anyway, ill start off with some basic maths.
P4 - quad pumped bus. Take my 2.8b for example - its running on a 133mhz bus at an internal clock of 4 x 133 or 533mhz.
Add dual DDR into the equation. Dual ddr running at 133mhz would be running at 133 x 2 (ddr) x 2 (dual bank) for a total of 533mhz.
Now imagine if you will dual ddr running at not 133mhz, but 166mhz using a 4:5 divider. This would give 166 x 2 x 2 for 666mhz. 133mhz of wasted bandwidth.
What concerns me is that dividers will become pointless. We can see from experience with AMD cpus that running the memory bandwidth higher than cpu bandwidth offers little to no gain at all.
What this means for the P4 and our DDR is that the new generation of high multiplier P4s will be wasted on our current ddr memory. The 166mhz bus may help intel, but it wont be the answer as far as were concerned. Back with a 1:1 ratio again well be hitting AMD syndrome - ie needing ultra high FSBs so we can get the memory bandwidth right up there. A lot of people round here are running their DDR on their intel systems between 220 and 250mhz, meaning FSBs of 220 to 250mhz to get the most out of the memory. This is simply impossibel with 100 or 133mhz P4s. Itll be bloody hard to get with a 166mhz P4 as well.
A P4 2.66 on the 166mhz bus speed would have a 16x multiplier. With these chips easily hitting 3.5ghz well take this figure as our projected O/C. 3500 / 16 = 219 mhz. Not a bad bus speed, but quite a lot lower than many of us are able to achieve with our memory. If my sources are correct, the 2.66ghz P4 will be the slowest P4 available on a 166mhz bus. A shame really, as something like a 2.4 P4 on 166mhz bus with C1 stepping could see us all the way up to 230mhz or higher.
Anyway, the real point of this post. Intels overclocking yields increase slower than their multiplier. What I mean by this is that as the ceiling on the o/c increases, so does the multiplier, which means overall the FSB gets lower. For example - a 2.26b will o/c to say 3.2ghz. This gives a 188mhz fsb. a 2.8b will o/c up to 3.6ghz. However, this gives a 171mhz fsb. FSB is lower, cpu speed is higher. With the dual ddr chipsets it wont really be worth running ddr higher than FSB as itll be more bandwidth than the cpu can use. This would mean that out example 2.8b would have memory running at 171 x 2 x 2 for 682mhz overall, whereas the memory sticks themselvs are capable of running 230 x 2 x 2 for 920mhz. What a waste!
Fair enough we will still see a performance gain from running at this speed compared to single channel DDR. we would have an effective 682mhz instead of 460mhz using single channel and a 3:4 ratio. Itll just be a total waste of bandwidth to run it this low when its capable of so much more. I cant see dual ddr peaking on performance when oc/d until we see a low multiplier (preferably 15x for 2.5ghz, but as I said above, if my sources are right 16x is as low as we will see) 166mhz part comes out.
As intels clock speeds increase though, so will their multiplier. a 3Ghz 166mhz cpu would have an 18x divider. If this cpu was capable of 3.7ghz (more than our example 2.66 above) it would run at 205mhz. A substantial decrease in memory bandwidth. Under these circumstances I would bet on the 2.66 @ 3.5 / 220mhz to beat it in every benchmark due to the massive gain in memory speed. 60mhz memory difference will give more performance than 200mhz cpu speed afterall!
Anyway, said enough for now. Back to fighting with my IT7 :).
PiLsY.
Thought id share a few thoughts on Dual DDR for the P4. Over the next month well be seeing dual ddr chipsets from Via and SiS. Theyre both schedules for a late october release, so its sooner than you think :). The Intel Granite Bay dual ddr chipset is due out late november, so a way to go for intel yet. Anyway, ill start off with some basic maths.
P4 - quad pumped bus. Take my 2.8b for example - its running on a 133mhz bus at an internal clock of 4 x 133 or 533mhz.
Add dual DDR into the equation. Dual ddr running at 133mhz would be running at 133 x 2 (ddr) x 2 (dual bank) for a total of 533mhz.
Now imagine if you will dual ddr running at not 133mhz, but 166mhz using a 4:5 divider. This would give 166 x 2 x 2 for 666mhz. 133mhz of wasted bandwidth.
What concerns me is that dividers will become pointless. We can see from experience with AMD cpus that running the memory bandwidth higher than cpu bandwidth offers little to no gain at all.
What this means for the P4 and our DDR is that the new generation of high multiplier P4s will be wasted on our current ddr memory. The 166mhz bus may help intel, but it wont be the answer as far as were concerned. Back with a 1:1 ratio again well be hitting AMD syndrome - ie needing ultra high FSBs so we can get the memory bandwidth right up there. A lot of people round here are running their DDR on their intel systems between 220 and 250mhz, meaning FSBs of 220 to 250mhz to get the most out of the memory. This is simply impossibel with 100 or 133mhz P4s. Itll be bloody hard to get with a 166mhz P4 as well.
A P4 2.66 on the 166mhz bus speed would have a 16x multiplier. With these chips easily hitting 3.5ghz well take this figure as our projected O/C. 3500 / 16 = 219 mhz. Not a bad bus speed, but quite a lot lower than many of us are able to achieve with our memory. If my sources are correct, the 2.66ghz P4 will be the slowest P4 available on a 166mhz bus. A shame really, as something like a 2.4 P4 on 166mhz bus with C1 stepping could see us all the way up to 230mhz or higher.
Anyway, the real point of this post. Intels overclocking yields increase slower than their multiplier. What I mean by this is that as the ceiling on the o/c increases, so does the multiplier, which means overall the FSB gets lower. For example - a 2.26b will o/c to say 3.2ghz. This gives a 188mhz fsb. a 2.8b will o/c up to 3.6ghz. However, this gives a 171mhz fsb. FSB is lower, cpu speed is higher. With the dual ddr chipsets it wont really be worth running ddr higher than FSB as itll be more bandwidth than the cpu can use. This would mean that out example 2.8b would have memory running at 171 x 2 x 2 for 682mhz overall, whereas the memory sticks themselvs are capable of running 230 x 2 x 2 for 920mhz. What a waste!
Fair enough we will still see a performance gain from running at this speed compared to single channel DDR. we would have an effective 682mhz instead of 460mhz using single channel and a 3:4 ratio. Itll just be a total waste of bandwidth to run it this low when its capable of so much more. I cant see dual ddr peaking on performance when oc/d until we see a low multiplier (preferably 15x for 2.5ghz, but as I said above, if my sources are right 16x is as low as we will see) 166mhz part comes out.
As intels clock speeds increase though, so will their multiplier. a 3Ghz 166mhz cpu would have an 18x divider. If this cpu was capable of 3.7ghz (more than our example 2.66 above) it would run at 205mhz. A substantial decrease in memory bandwidth. Under these circumstances I would bet on the 2.66 @ 3.5 / 220mhz to beat it in every benchmark due to the massive gain in memory speed. 60mhz memory difference will give more performance than 200mhz cpu speed afterall!
Anyway, said enough for now. Back to fighting with my IT7 :).
PiLsY.