[News] AMD Socket AM4 Photo surfaced

[StyM]

http://www.guru3d.com/news-story/amd-socket-am4-photo-surfaced.html


Both AMD Bristol and Summit ridge processors are to be seated onto a Socket AM4 motherboard. Bristol ridge is based on last gen architecture, Summit ridge is the new 8-core ZEN processor. Photos of that new Socket AM4 have surfaced.

From the looks of the the new socket will get more pins (1331) whereas the older AM3+ had 942. Other then that the retention mechanism and design look rather similar as well as its size at 40x40mm. It is still a little unclear whether or not coolers are compatible with previous-generation AM2, AM3, AM3+, FM2, FM2+ coolers with. Some manufacturers have claimed compatibility, while other have reported to be offering AM4 CPU cooler upgrade kits.

The extra pins will be needed for DDR4 memory (dual channel, up-to 3200 MHz) and obviously the integrated nortbridge that resides in the upcoming processors. We extaect to see the first AM4 motherbaords once Bristol Ridge become available, Summit Ridge (ZEN) is expected to launch in Q1 2017.



http://www.guru3d.com/index.php?ct=news&action=file&id=16512
http://www.guru3d.com/index.php?ct=news&action=file&id=16513

[AliG]

I'm really curious why they needed to increase the pin count so much. Intel has supported DDR4 for a while and they don't need nearly that many.

Perhaps its in preparation for HBM? As I understand it, their Zen based APUs will share HBM between CPU and GPU.

[Kai Robinson]

The reason why is because the APU's are a total SoC - the extra pins will no doubt be for connecting to all the PHY's, plus it's expected that the Zen HEDT chips will offer 24 PCIe lanes (Skylake is 20 PCIe lanes).

[Darakian]

As an SoC it should need fewer pins though right? I mean with everything on chip what is there to connect out to?

[Greg83]

a soc. on chip usb. don't need to add latency of the pci-e bus and lanes, to produce things like Network interface, usb ports. these things are directly connected into co processors on the cpu die.
with zen this may be even connected to the cpu , if not come zen+ through coherent fabric serial communication layer, instead of through pci-e controller on die. like with former apu's where HTT was replaced with pci-e for those things.
cause htt bus was dropped outside of fx series as an innterconnection chipset to cpu, to an external pci-e controller .
so yes, instead of pci-e lane pins, which can be used for pci-e. soc's still need pins for the co processors it is hosting on die. so for usb , it needs 1 pin per usb pin co processor. if that co processor can handle 8 usb ports in port multiplier, it will require the 2 pins for usb ports on the SOC, the send and receive the + and the - , the serial, while the rest is just to PWM of the motherboard for the hydro side and grounding. once at the physical usb port.
with something like a network card. a on soc nic, will likely use pci-e interfacing method still, and there is again, just 1 + and 1 minus, send and receive, despite having 8 pins again with networking interfaces, with some being dedicated grounding and shielding and poE . the other 6 wires were for data, all merged into again, send and receive, 2 pins on the SOC.

anyway 4 pins for usb and network interface , for a lower end APU. while things like ZEN HPC processors, could have upto 8 pins on the cpu SOC, still for things like 10Gbit networking, depending on how its been accomplished, if its like a vlan of multiple networking interfaces like how sata 3Gbps was done with the 990fx southbridge to produce a makeshift sata 6gbps controller .

oh and then, there will be the m2.sata connecting directly to the arm co processor. repeating the need for seperate arm controllers to produce a storage controller, so m2.sata can be operated with arm processor on SOC , identically to how NVDIMMS can operate as storage controllers or non violitile dram.

biggest changes in performances will come from these new direct to cpu pins. for external devices. even desktop ZEN's will just have more controllers for other things, in the extra GPU interconnection space. with only a few little things going on the off cpu chipset. which won't be worth very much to improve performances of. like sata 6gbps.

while even direct to cpu and arm co processor on cpu, will accelerate and make cheaper m2.nvram storage devices w/o a co processor and just pure nand. plus its also the linux subsystem on die with arm that is gonna also be handing the dram encyption in real time for amd zens, producing that data security they were talking about in the slides.

[zanzabar]

The reason why is because the APU's are a total SoC - the extra pins will no doubt be for connecting to all the PHY's, plus it's expected that the Zen HEDT chips will offer 24 PCIe lanes (Skylake is 20 PCIe lanes).

isnt skylake 16pci-e lanes on the cpu? the next tik gets 20.

[AliG]

The reason why is because the APU's are a total SoC - the extra pins will no doubt be for connecting to all the PHY's, plus it's expected that the Zen HEDT chips will offer 24 PCIe lanes (Skylake is 20 PCIe lanes).

Very interesting. I assume they're adding the extra PCI_E lanes for heterogenous cloud computing? As far as I recall, most gaming tests shows there's really no benefit to go from 8x to 16x.