How do you work out the CPU:DRAM divider (A64) ?

[GreenBeret]

I initially thought that the 200Mhz,166Mhz, 133Mhz and 100Mhz in the Shuttle BIOS will set the RAM to run at 1:1, 5:6, 2:3 and 1:2 of the HTT speed, but I was wrong. It seems that the CPU:DRAM divider (CPU/11, CPU/12, CPu/13 etc.. see CPU-Z for details) is also dependent on the CPU multiplier... Anyway atm my guess is that the RAM Mhz setting in the Shuttle AN50R BIOS refers to the maximum MHz of the RAM with regards to the FSB, and then the system picks a CPU: DRAM divider so that the RAM MHz is derived from the CPU clock speed AND it should be closest to the max RAM MHz.... makes sense ? :p It's 1AM so my mind may not be working properly :p

I've been searching forums and google all night but haven't found any info on this yet. Hope someone here can provide some info :) Thanks in advance :)

[CodeRed]

Niko,

Its pretty simple once you know how the DRAM frequency is worked out. First the DRAM frequency is derived off the CPU clock frequency and the DRAM multiplier (or divisor depending on how you look at it).

DRAM Frequency = CPU Clock Frequency / DRAM Divisor

The DRAM Divisor is calculated by the DRAM controller based on the CPU multiplier and the DRAM Speed setting in one of its control registers. Normally the DRAM Divisor is an integer value, with the exception of 1:1 ratio and 0.5x CPU multipliers.

Anyway here's the table of DRAM Divisors vs CPU multipliers and DRAM speed settings



+------------------------------------------+
| CPU Multi | DRAM Divisor |
| | 200 166 133 100 |
+--------------+---------------------------+
| 10x | 10 12 15 20 |
| 9.5x | 9.5 12 14 19 |
| 9x | 9 11 14 18 |
| 8.5x | 8.5 11 13 17 |
| 8x | 8 10 12 16 |
| 7.5x | 7.5 9 11 15 |
| 7x | 7 9 11 14 |
+--------------+---------------------------+



These values were generated using the results from CPU-Z ... I hope they are correct ;)

Note that the DRAM frequencies are as close as possible to the desired values of 200,166,133, or 100 (without exceeding them) for each CPu multiplier option.

Shame AMD didnt allow for direct DRAM divisor manipulation .. that would open up all sorts of possibilities ... need to investigate the reserved DRAM speed codes ;)

[Penti]

Thats right CodeRed, heres a thread i replyed in on the subject a few months ago. Just wrote what the divider for DDR333 would be, and what the freq would end up being though. http://www.xtremesystems.org/forums/showthread.php?postid=282317#post282317

Regards
Penti