Some Fermi details from John Chen at IEDM2009

[Hans de Vries]

3.2 billion transistors on a 20x20mm die.
http://www.semiconductor.net/article/438968-Nvidia_s_Chen_Calls_for_Zero_Via_Defects-full.php

Regards, Hans

[fellix_bg]

3.2B trannies on 400mm² -- they must really take care for every last defect and leakage watt of such high IC density!

[spursindonesia]

Umm, a 730 mil transistor GT 215 is around 140 mm^2 in 40 nm node, then we should believe a 3.2 bil transistor Fermi would be just less than three times bigger ? Does Fermi consist of only cache ??

[LedHed]

what does Chen mean by this:
"DC power has exceeded AC power for the first time,"

[K404]

~130W????

I think theres more than one part being discussed in there :p:



Chen said Nvidia's 40 nm graphics processor has 3.2 billion transistors........ Although (design tricks) have kept Nvidia's 20 × 20 mm die within a ~130 W power envelope, the big concern is leakage current.

[LedHed]

and is this to make us believe the chips will actually be stacked?


"Assuming a 3-D die stacking process can yield reasonably well, the net yield and the associated cost can be a significant advantage," he said. "This is particularly true in the case of hybrid integration of different chips such as DRAM and logic, which are manufactured by very different processes."

[Helloworld_98]

this article is full of fail

unless 'fermi' is now a bunch of GT315 stacked on each other.

[Nedjo]

wow this article is so resourceful:

What's wrong with TSMC's 40nm tech (I'd love to read more "down-to-Earth" clarification from Hans if possible):



Chen's speech included a call to "my friends at TSMC to give me more 40 nm parts," and a plea for improved via defectivity. :banana::banana::banana::banana: James, a technology analyst at Chipworks (Ottowa, Canada), said via defects have shown up on ICs manufactured by TSMC. Chipworks has inspected products from graphics vendor ATI, now part of Advanced Micro Devices (AMD, Sunnyvale, Calif.). "The problem appears to be that when they cut a via, a residue of photoresist gets on the edge of the via, which creates a ring-shaped discontinuity in the metal," James said. "The discontinuity could create electromigration issues. We've seen the same problem on the upper metal levels on the ATI chips we've studied. It creates a reliability failure mode."

NVIDIA eying SOI tech (we still remember recent "NO" to GloFo from the Jensen ;) ):



A marketing manager at Chartered Semiconductor Ltd. (Singapore) said Nvidia is investigating silicon-on-insulator (SOI) technology, which Chartered and GlobalFoundries both provide. Nvidia joined the SOI Consortium (Boston) last summer. James of Chipworks said the buried oxide layer in an SOI substrate could reduce current leakage by blocking leakage from an active area to the bulk silicon. "SOI could take out a whole leakage mechanism," James said.

SLi on die???!



Nvidia also needs through-silicon vias (TSVs) so that it can connect its logic transistors to DRAMs on a separate die. With 3-D interconnects, it can vertically connect two much smaller die. Graphics performance depends in part on the bandwidth for uploading from a buffer to a DRAM. "If we could put the DRAM on top of the GPU, that would be wonderful," Chen said. "Instead of by-32 or by-64 bandwidth, we could increase the bandwidth to more than a thousand and load the buffer in one shot."

why is dependence on binning such an issue:



Variation is hurting the company's business, which depends on binning. The normal practice is to bin the best chips to the ultrahigh-performance accounts, devices that hit the mean performance and operating voltage metrics to the notebook market, and slightly underperforming chips to desktops. "The problem if the mean of the variation shifts day to day, we lose all of our ultra and some of our mobile bin," Chen said. "It creates a huge inventory of desktop chips, some of which we have to discard. This is really going to be a major problem at 28/22 and beyond. Even 1 nm variation in a CD can affect our products in a very significant way."

again this is fantastic article and the first real piece of info what's really causing Fermi delays!

[highoctane]

I don't think he was directly trying to say fermi itself as being 20x20 mm2, but talking about process size in general, leakage, etc and how important the process is.

Just happened to mention fermi as 3.2b in relation to the rest of the topic.

[Nedjo]

I don't think he was directly trying to say fermi itself as being 20x20 mm2, but talking about process size in general, leakage, etc and how important the process is.

Just happened to mention fermi as 3.2b in relation to the rest of the topic.
well there's a way for Fermi to be 20x20 chip with 3.2b transistors:

two 20x20 dies with 1.6b transistors each!

it really makes sense, and explains difficulties in bringing out this in fashionable time-frame

[ajaidev]

So fermi leaks big deal so does 5870, I am very interested in the DRAM on top of the GPU idea. AMD did an opposite with its llano cpu that has no L3, may be the added bandwidth is not worth the extra die area by AMDs std's but sure seems important to Nvidia.

[zalbard]

130W having 50% more transistors than 5870? I'm never gonna believe that.

[Helmore]

130W having 50% more transistors than 5870? I'm never gonna believe that.

You don't have to, you simply misread the article. The only thing the article says about Fermi is the amount of transistors the chip has. It doesn't state any die size or power consumption for Fermi.

One interesting thing I noticed in the article. NVIDIA part of the SOI consortium? I didn't know that.

[Manicdan]

if the 3.2b part is right, what kind of chip size are we expecting here? (based on the 200 series)

[Mechromancer]

130W having 50% more transistors than 5870? I'm never gonna believe that.

But it's Nvidia. Nvidia would never lie to us. How dare you question Jen Hsun :mad:.

[zalbard]

You don't have to, you simply misread the article.Ah, my bad. I suppose it refers to 90nm then? Not sure I get it right, my English fails me sometimes.

[Chumbucket843]

well there's a way for Fermi to be 20x20 chip with 3.2b transistors:

two 20x20 dies with 1.6b transistors each!

it really makes sense, and explains difficulties in bringing out this in fashionable time-frame

its one die with 3.2 billion transistors.

[***Deimos***]

what does Chen mean by this:

DC power higher than AC...

the short answer is that they are saying static power (gate leakage) is higher than dynamic power (current flow when switching).

Almost all chips use CMOS. There are two types of transistors PMOS (source and drain doped "positive") and NMOS ("negative".. also much faster). For some simple logic gate like "OR" there is a pull-up to Vcc and matching pull-down network to ground. Hence "COMPLEMENTARY" in CMOS. But in static CMOS (ie SRAM cache) there is always path to ground or Vcc, so for dynamic logic, value of circuit (0 or 1 ) is only evaluated when clock signal is set.

In ideal world transistor is like valve on garden hose. When you open it, all the water flows through hose. When you close it, no water leaks out. But, imagine its cheap Walmart valve made of cheap plastic instead of metal. All that water pressure behind the valve breaks through in little leaks, and your well pressed Sunday pants get all wet. A little leaking water wont harm the grass, but imagine 3 000 000 000 leaking valves!

Now more water is leaking overnight than when you get clock signal (wife yells!) and you briefly turn the valve on and off. :shocked:

Each die shrink, the "valve" is smaller and smaller, and yet has to hold back all this pressure. Thats what all the "high-K dielectric" talk is about - a better insulator between gate and channel. :up:

FYI in eetimes read TSMC 40nm problem is due to issues with immersion lithography (liquid under lens to focus better), and the silicon straining used to improve hole/e- mobility.

Please correct if my undergrad memory is off.
:shrug:

[Tao~]

^ thats some stuff i'd like to learn ;)
thx mate :up:

[LordEC911]

if the 3.2b part is right, what kind of chip size are we expecting here? (based on the 200 series)
Very close to G200... ~500-550mm2.

[***Deimos***]

Very close to G200... ~500-550mm2.

or maybe quite a bit smaller... maybe indeed in the 400 range. Maybe the 20x20 rumored was approximation. Maybe 21x22=462?

- I dont think anybody really knows exactly how many transistors. Usually approximated based on #of logic gates (ie AND, XOR, NOT).

- all types of circuit/logic don't scale exactly with smaller process. Intel has recently proved that with record small SRAM cells in 22nm (not typo).

- if Fermi has a lot of compact cache, buffers etc, then chip may be smaller. Can also be from better layout optimization. Very well possible that the long 19 month span since G200 was well used to squeeze down every mm^2. AMD has already used aggressive optimized logic/circuit libraries for years.

- ofcourse, as everybody knows G200 was completely different architecture.
from the best of my knowledge, there is NO DIE SCREENSHOT, and no official word on size or yields.

[LordEC911]

or maybe quite a bit smaller... maybe indeed in the 400 range. Maybe the 20x20 rumored was approximation. Maybe 21x22=462?

- I dont think anybody really knows exactly how many transistors. Usually approximated based on #of logic gates (ie AND, XOR, NOT).

- all types of circuit/logic don't scale exactly with smaller process. Intel has recently proved that with record small SRAM cells in 22nm (not typo).

- if Fermi has a lot of compact cache, buffers etc, then chip may be smaller. Can also be from better layout optimization. Very well possible that the long 19 month span since G200 was well used to squeeze down every mm^2. AMD has already used aggressive optimized logic/circuit libraries for years.

- ofcourse, as everybody knows G200 was completely different architecture.
from the best of my knowledge, there is NO DIE SCREENSHOT, and no official word on size or yields.
No, just... no.

[Jamesrt2004]

what does Chen mean by this:

lol probably means they gone over pci-e specs, so external power maybe :confused::shrug:

[mikeyakame]

I believe 130W TDP is gpu die alone on performance mode for low power 3d at 400/800/300. That would be the only way the chip would sneak under a 130W TDP really. At full power 3d there is no chance it would be a 130W TDP, and because Windows can operate at low power 3d it would make sense. I might be completely off here, but that's just a stab in the dark.