First 3-D processor runs at 1.4 Ghz on new architecture

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September 15, 2008 -- The next major advance in computer processors will likely be the move from today's two-dimensional chips to three-dimensional circuits, and the first three-dimensional synchronization circuitry is now running at 1.4 gigahertz at the University of Rochester.

Unlike past attempts at 3-D chips, the Rochester chip is not simply a number of regular processors stacked on top of one another. It was designed and built specifically to optimize all key processing functions vertically, through multiple layers of processors, the same way ordinary chips optimize functions horizontally. The design means tasks such as synchronicity, power distribution, and long-distance signaling are all fully functioning in three dimensions for the first time.

"I call it a cube now, because it's not just a chip anymore," says Eby Friedman, Distinguished Professor of Electrical and Computer Engineering at Rochester and faculty director of the pro of the processor. "This is the way computing is going to have to be done in the future. When the chips are flush against each other, they can do things you could never do with a regular 2D chip."

http://www.design-reuse.com/news/19080/3-d-processor.html

[Hell Hound]

Show it to me.I guess mobo will be like a platform for you to stack chips like lego blocks.

[Warboy]

Interesting...Cubes for chips, Cubed memory next?

[RaZz!]

if the processor consists of multiple layers (vertically), how is one supposed to cool that thing? or: how are their plans to cool the lower layers of the processor?

[FischOderAal]

if the processor consists of multiple layers (vertically), how is one supposed to cool that thing? or: how are their plans to cool the lower layers of the processor?

Exactly what I was wondering too.

[Star_Hunter]

if the processor consists of multiple layers (vertically), how is one supposed to cool that thing? or: how are their plans to cool the lower layers of the processor?

I think they are doing it with micro water jets within the cube (or diff fluid).

[Hornet331]

hows die stacking actually "new"? :p:

[MarlboroMan]

if the processor consists of multiple layers (vertically), how is one supposed to cool that thing? or: how are their plans to cool the lower layers of the processor?

nano-Peltier ;)

[cryomonkey]

if the processor consists of multiple layers (vertically), how is one supposed to cool that thing? or: how are their plans to cool the lower layers of the processor?

Exactly, heat density ... I thought that was the reason they went to multi-core design in the first place. Not to mention like you pointed out the layers above would in effect insulate the layers below.

[paulhamm]

Something tells me they need to spend a lot more time on high temp super conductors or these things will simply vaporize when you flip the power on. Thermal layers between the electrical layers that have been micro perforated for the traces between levels. Only way it might work that I can think of to keep it cool today.

[zanzabar]

Interesting...Cubes for chips, Cubed memory next?

that was 1st remember zram

[WangChung]

I would think that people developing next gen microprocessors and working in an applied material science would understand the fundamental basics of thermodynamics. Pretty sure they got it under control guys. :p:

[Warboy]

that was 1st remember zram

Not quiet what I had in mind.

[Blauhung]

I think one of the cool possibilities of this was being able to stack cache directly on top of execution cores. You can really cut down on the die footprint and greatly shorten trace length to the data the cores need.

[largon]

This isn't about stacking silicon chips.
It's about stacking logic inside a single silicon chip. To date all logic and cache and what-not has been laid out in a single 2D plane - basically all CPUs and GPUs are 2-dimensional thinner-than-hair layers of logic. Getting these "3D chips" to work would enable multiplication of transistor density per mm² of silicon. Unlike stacked silicon, stacked logic doesn't yield a huge thermal problem as there's still just one "layer of rock" to cool.

[ABXG]

I guess for cooling there might integrated heat pipes. I think this is a really great thing to happen as it would allow for construction of circuit boards in 3d, allowing for much more compact designs. I would eventually like to see this used to make PC's where the motherboard is basically a cube with cube like slots for all the components to fit in. In this way your entire PC would be a rather compact cube. The problem would be cooling such a monster, but integrated water cooling could solve this.

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largon sum it all up

if you notice in the article it is not about stacking it is about able to communicate vertically and horizontally 3D communication from what I read stacking is just piling silicon layer over another layer

[KoHaN69]

but the yield would be geometrically lower than 2D chips :shrug:

[RaZz!]

I would think that people developing next gen microprocessors and working in an applied material science would understand the fundamental basics of thermodynamics. Pretty sure they got it under control guys. :p:

nobody questioned the developer's knowledge or skills, it was more an attempt to understand how such an architecture is being cooled ;)

[SnipingWaste]

:wasntme:

[Hell Hound]

Is it dual core vertical or something.sounds like it.

[AliG]

eitherway, even if the architecture is crap, that wasn't their goal, it was just to make a successful attempt at designing a 3d chip (in such a sense that there are multiple processors for each logic functions), this can greatly improve multi-threaded performance, or even singlethreaded if I'm thinking of it properly, since that means that the each "core" can run much more commands per thread

What that means is that now intel and amd have to find some way of bringing this technology to desktop use if we want it, but I personally think x86 should be droppped for that to happen, we seem to be hitting its limits (and don't even get started about arguing about that, you'll just waste everyone's time)

[initialised]

Interesting...Cubes for chips, Cubed memory next?Flash memory is routinely die stacked (die on die), z-RAM looks set to replace DRAM in the near future and is easier to stack than DRAM, double sided DIMMs can be thought of as die stacked. Basically any processor or storage I/O sections are concentrated on the edges can be die stacked, expect to see it in many 32nm products. But enough on die stacking and back to 3DICs

I believe IBM and Intel are working on stacked CMOS structures (n-type on top of p-type or vice-versa) for use in processors and SRAM (CPU cache) which may overcome some of the areal limitation faced by the 32nm node, not quite a 3DIC but a big gain in density.

[AliG]

either way, this is stacked logic, not stacked dies, so zram technology vastly differs and it is to do so with ram because they produce so little heat and don't require much power anyways (no power envelopes to worry about)