MARS mobo and domminator8888c4d ram question

[HDCHOPPER]

http://www.hexus.net/content/item.php?item=6634&page=2

will this ram run on the MARS sham or saaya ??

think it will if overclocked but just dont know for shure :D

anyone pipe in if you know please :up:

[HDCHOPPER]

ok well just picked these 2 X 1 gig sticks up from another forum for 100 bucks !

should be here within the week guess eye will find out the hard way :D

cant believe eye did it heck my Firestix's do 1200 but at cas 5

hopeing these will do 1200 at least on cas 4 :yepp:

[HDCHOPPER]

ok got them in and cant get cas 4 even tho thier rated for it :confused:
eye set tRFC 59 & enabled fast chip slect manullay in bios loose enough to get anything hopefully :rolleyes: left rest on auto just to see id cas 4 would pop up in windows ... it didnt :(
next tried cas 4 manullay no go .. can slect cas 5-4-4-4-15 but not 4-4-4-15 let alone 4-4-4-12:mad: and ya eye am putting 2.4 volts into em for all this

heres a screenie maybe some one can help me here :D

# 1 how do eye enable EPP function on the MARS ( if one can?)
# 2 different mem dividers gives me the same jedec numbers why
# 3 eye want those EPP numbers !!! HELP
# 4 will using the mem channell I0 DLL adj & mem channell I1 DLL adj stuff help? ( never touched em cause really dont know how to correctly )...thay go +1+2+3 ect... what do thay do?


click to enlarge:....

http://img4.glowfoto.com/images/2008/09/18-0213137226T.jpg (http://www.glowfoto.com/viewimage.php?img=18-021313L&y=2008&m=09&t=jpg&rand=7226&srv=img4)

stastic:..http://www.glowfoto.com/viewimage.php?y=2008&m=09&img=18-021313L&t=jpg&rand=7226&srv=img4

[HDCHOPPER]

ok after all night finally got my cas 4 ( had to jack up fsb.. a lot)

but still would like to know about the mem channell I0 &I1 DLL settings adj

Claims:What is claimed is:

1. A semiconductor memory device comprising: an anti-fuse block having a plurality of anti-fuses for writing thereinto data required to adjust a timing of an internal signal generated when an initial setting is made; a delay amount switching circuit for delaying the internal signal by a desired delay amount in accordance with the data; a latch circuit for generating a command required to read the data from said anti-fuse block based on the internal signal delivered from said delay amount switching circuit after the delay; and a DLL reset signal generating circuit for supplying said anti-fuse block with a DLL reset signal generated by using the command signal and a reset signal supplied asynchronously to a clock for causing said anti-fuse block to deliver the data.

2. The device according to claim 1, wherein the DLL reset signal generating circuit is adapted to generate the DLL reset signal based on a PMDCMDT signal supplied from the latch circuit.

3. The device according to claim 1, wherein the DLL reset signal generating circuit is adapted to receive instructions in accordance with values of a PMRS signal and an ADD2 signal which are code signals.

4. The device according to claim 1, wherein the DLL reset signal generating circuit is adapted to deliver the DLL reset signal when applied with a reset signal asynchronous to clock CLK, which is supplied from outside during a period of powering on a system generating a MRS CMD signal employed in a DDR3-SDRAM.

5. A method of adjusting a semiconductor memory device for adjusting a timing of an internal signal by using data written into anti-fuses when an initial setting is made, said method comprising the steps of: asynchronously generating a DLL Reset signal for delivering the data from said anti-fuses by using a reset signal supplied asynchronously to a clock; and supplying the DLL Reset signal to an anti-fuse block including a plurality of anti-fuses which have data written therein required for adjusting the timing of the internal signal.

6. The method according to claim 5, wherein the DLL reset signal is generated based on a PMDCMDT signal supplied from a latch circuit.

7. The method according to claim 5, wherein the DLL reset signal is generated using a DLL reset signal generating circuit adapted to generate the DLL reset signal based on a PMDCMDT signal supplied from a latch circuit.

8. The method according to claim 5, wherein the DLL reset signal is generated using a DLL reset signal generating circuit adapted to deliver the DLL reset signal when applied with a reset signal asynchronous to clock CLK, which is supplied from outside during a period of powering on a system generating a MRS CMD signal employed in a DDR3-SDRAM.

9. A method of adjusting a semiconductor device for adjusting the timing of an internal signal by using data written into anti-fuses when an initial setting is made, said method comprising the steps of: reading data written into the anti-fuses included in said semiconductor device by using a command signal generated within said semiconductor device, and a reset signal supplied asynchronously to a clock signal; and adjusting the timing of the internal signal in accordance with the data.

10. The method according to claim 9, wherein the reset signal is generated based on a PMDCMDT signal supplied from a latch circuit.

11. The method according to claim 9, wherein the reset signal is generated using a DLL reset signal generating circuit adapted to generate the DLL reset signal based on a PMDCMDT signal supplied from a latch circuit.

12. The method according to claim 9, wherein the reset signal is generated using a DLL reset signal generating circuit adapted to deliver the DLL reset signal when applied with a reset signal asynchronous to clock CLK, which is supplied from outside during a period of powering on a system generating a MRS CMD signal employed in a DDR3-SDRAM.

read this and understud it but ... what does it effect & help to everyday MARS overclocking :)

anyone ... anyone ..... buler....buler .....fry....fry......hehheheheheehheee

[HDCHOPPER]

what does it really do or turn on ? does it have to do with EPP profiles ???

on the memory page in bios
thiers a fast chip slect ... auto/enable /disable

also memory channell I0 DLL adj setting .. what will this do/ help ???
and memory channell I1 DLL adj setting ...what will this do/help ?? for overclocking or stability ???

[HDCHOPPER]

ok what is this a bad question ???

com'on yall

are corsair bad ram for QuatumForce boards????

[Harshal]

Not sure about that model but I have Corsair 9136C5D and it works fine.. super fine infact!
But no DLL adjust here. Simply punch in the timings you want [say 4-4-4-8] and boot @ 2.45-2.55V
http://www.imgx.org/files/19811_lihkr/32M_3368_1155%20%28L%29.JPG

[HDCHOPPER]

thank you harshal ! thats pretty darn good for c5 sticks !!

finally got them to run cas4 stable at 1069 but really wanted to see 1111 or 1200 still worken it

at: memset
4
4
4
4
12
4
59
8
20
17
5
8
5
4
2600T
2T

(putting a check mark in auto in memset with 444412 manualy set and the rest memset set)

[HDCHOPPER]

ok rolled back to MARS G@^ bios to see if it would reconize the EPP profiles of this ram

nope it didnt same as G29 & G28 would going to G30 help???

really like this ram it will do cas 3 but gotta down the fsb big time to do it but cas 4 works only on 1:2 divider which = 1-1 try anything else and it's a round of changeing ram to post again before eye can put them back in
need zippers on my case :D

whats with not reconizeing the EPP profiles saaya????