Why does CAS and latency increase with memory speed?

[virtualrain]

As memory speeds increase, CAS and latency seem to increase. I'm interested in a technical explanation of why that's the case. Maybe someone can reference some technical reading or provide a technical overview of the memory read/write process at a high level?

It would seem to me that the cycles required to initiate a transfer to/from memory should be the same regardless of the frequency of the modules or the bus.

Thanks,
-Chris.

[cadaveca]

the avg mb/sec will stay consistent when timings change. Modules have a limit they can handle..increasing the bus speed, however, gets the data to the ram faster, but it still is subject to having max mb/sec it can handle.

[virtualrain]

the avg mb/sec will stay consistent when timings change. Modules have a limit they can handle..increasing the bus speed, however, gets the data to the ram faster, but it still is subject to having max mb/sec it can handle.

So if RAM that's running as DDR2-400 takes 4 cycles to ready a read command (CAS 4) and the memory modules are running at 100MHz, that 4 cycles translates to 4ns.

Now if you take that same RAM at run it at DDR2-800 speeds, it still takes 4ns to process the read command but since the memory is running at 200MHz, the 4ns is now equivalent to 8 clock cycles. So if this memory is sold at this speed, would it be rated at CAS8?

I'm still missing something here.

Can anyone get into this in a bit more detail?

[cadaveca]

AS you increase the speed, the overall functionality of the mem is increased. Small increases in FSB, dependant on timings, can increase bandwidth hugely...enough so that the IC would end up closing pages early, maybe not finish a read...

And yeah, you seem to get the jist of it. Of course, it's far more convoluted than that, but in the end, if timings were not loosened as speed increases, the modules would not be able to keep up.


MAybe hit Saaya up in a PM, or something, as I'm sure he'll have some answers for u.

[virtualrain]

I think I got it now... The physical delay of the memory cells is not something that can be changed... so as frequency increases, the number of cycles spent waiting for the memory to read/write is going to increase even though the net delay is still the same which is the basic physical delay of the cells.

So, DDR2-800 at CAS4 has the exact same latency as DDR3-1600 at CAS8. Why do I hear so many people complaining that DDR3 latencies are so bad. They are the same are they not? Are these people mis-informed or am I missing something still?

[cadaveca]

I think because of latency limits of current DDR3 IC's that we see the complaints...I mean really..if we have DDR1600 @ CAS5...but we don't.

The memory controller plays a role too...but not that large.

[virtualrain]

I think because of latency limits of current DDR3 IC's that we see the complaints...I mean really..if we have DDR1600 @ CAS5...but we don't.

The memory controller plays a role too...but not that large.

The fastest DDR2-800 runs at CAS3 so it's unlikely you would ever see DDR3-1600 below CAS6. Since you can get DDR3-1600 at CAS7 which is really only like DDR2-800 CAS3.5, we aren't far off. Correct?

I think the biggest problem with DDR3 is the FSB bottleneck (http://www.nehalemnews.com/2008/05/editorial-need-for-imc-and-why-fsb-is.html).

[yankee]

I've done some searching around trying to see how ram timings are related to one another(e.g. how we get 4-4-4-12 or 5-5-5-15), and more interesting to me subtimings. I've searched a lot, and found the following links. Still nothing about subtimings. :(
Section on DRAM timings:
http://www.blazingpc.com/forum/showthread.php/explained_nb_fsb_sb_voltage-8907/index.html
Quite old, but the theory contained is still relevant.
http://www.pcguide.com/art/sdramTiming-c.html

I'll be watching this discussion very closely.

RAM timings are still one of man's great mysteries :D

[virtualrain]

I've done some searching around trying to see how ram timings are related to one another(e.g. how we get 4-4-4-12 or 5-5-5-15), and more interesting to me subtimings. I've searched a lot, and found the following links. Still nothing about subtimings. :(
Section on DRAM timings:
http://www.blazingpc.com/forum/showthread.php/explained_nb_fsb_sb_voltage-8907/index.html
Quite old, but the theory contained is still relevant.
http://www.pcguide.com/art/sdramTiming-c.html

I'll be watching this discussion very closely.

RAM timings are still one of man's great mysteries :D

That's good reference material... perhaps the best explanation of RAM operation I've seen! :up: