Tweaking Barcelona via WPCREDIT.

[Antinomy]

Hello.
I would like to present an article (http://people.overclockers.ru/antinomy/record11) about tweaking Barcelona via WPCREDIT. There are the main actions you should do to tweak almost any setting\timing in the Barclona and A64 in generaly integrated memory controller. And not only memory. The article is based on BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h Processors. There is a link to it in the article.

[dave_graham]

sounds good. I'll be working with this.

dave

[Lightman]

Good article!
I learned something new today :up: !

[tictac]

if you guys lazy for this hex code modding. you still can use felix memset tool. search it on this forum you would find it. most memory timing of barcelona same as am2 timing.. give it a go!

EDIT :
MemSet is a memory tweaker for:
-INTEL 815 845 855 865 875 915 925 945 946 955 965 975 & P35.
-AMD A64 ddr&ddr2.
-NVIDIA NForce2, NForce 650i & 680i.
-VIA KT266/333/400/600.

Here is the 3.3 version (for 2000 /XP /Vista 32&64 bits):
Download Link:
http://perso.orange.fr/Tweak-and-Coe/Download/MemSet.exe

[Antinomy]

Lightman, thanks. :)
tictac, this article has been written exactly because Memset has a limited set of timings\settings, and the WPCREDIT doesn't ;) It can tweak everything in PCI registers that can be tweaked, of course.
And I wasn't sure that it will work with a CPU that it doesn't know. Cause MCHbaredit (which has been written by the same guy, AFAIK) doesn't want to work on chipsets similar to supported ones, but with a different DevID. And that is a big minus for the program.

[FELIX]

->tictac: I just read datasheet for barcelona, and memset can work only if you use DDR2-800, not above.
If you use DDR2-1066 or DDR3, values are wrong. I need to update it in version 3.4.
If someone can send me a register dump with DDR2-1066 or DDR3, it's welcome. :)

->antinomy: MchbarEdit work only with Intel 9xx chipsets, I need to update it too, coming soon.

[STEvil]

any chance of 5000x chipset support comming? /ot ;)

[macci]

Please check page 61 of BKDG (2.8.1). By default the CPU is running in "Unganged mode" and you need to program DCT0 and DCT1 individually.

This means that if you want to change RAS to CAS (for example) you need to program BOTH: offset 088 (DCT0) and also 188 (DCT1).

If you check the document it says "F2x[1,0]88" - here 0 is referring to DCT0 and 1 is referreing to DCT1.

The current tools would probably program only DCT0.

[tictac]

;Processor Memory Controller node 0 (Bus : 0 , Device : 24 , Function : 2)
dtl_add equ 08000C288h ; DRAM Timing Low address
dth_add equ 08000C28Ch ; DRAM Timing High address
dcl_add equ 08000C290h ; DRAM Configuration Low address
dch_add equ 08000C294h ; DRAM Configuration High address
odc_add equ 08000C29Ch ; Output Driver Compensation address
dcm_add equ 08000C2A0h ; DRAM Controller Miscellaneous Data address

;Processor Memory Controller node 1 (Bus : 0 , Device : 25 , Function : 2)
dtl_add1 equ 08000CA88h ; DRAM Timing Low address
dth_add1 equ 08000CA8Ch ; DRAM Timing High address
dcl_add1 equ 08000CA90h ; DRAM Configuration Low address
odc_add equ 08000CA9Ch ; Output Driver Compensation address
dch_add1 equ 08000CA94h ; DRAM Configuration High address
dcm_add1 equ 08000CAA0h ; DRAM Controller Miscellaneous Data address

[Antinomy]

FELIX, let the BKDG help you ;) there's everything on setting correct values on DDR2-1066 and DDR3. I don't think that anyone wiil be able to send you such a dump soon. Don't forget, that only B stepping will be able to work with DDR2 at more than 667 (800\1066). Better read the datasheet, IMHO.
It doesn't work with all of the 9xx - thats the matter of fact ;) so this is why I ask. Can the check be bypassed? I'll wait, but if you need some help with the docs... ;)
STEvil 5000X has PCI registers, so can be tweaked by WPCREDIT using the datasheet (it's available). But you can't change the timings by software though ;) We've had a lot of discussion on Overclockers.ru forum on this theme.

[tictac]

->tictac: I just read datasheet for barcelona, and memset can work only if you use DDR2-800, not above.
If you use DDR2-1066 or DDR3, values are wrong. I need to update it in version 3.4.
If someone can send me a register dump with DDR2-1066 or DDR3, it's welcome. :)

->antinomy: MchbarEdit work only with Intel 9xx chipsets, I need to update it too, coming soon.

Phenom X4 dump

Host Bridge
bus 0 (0x00), device 24 (0x18), function 2 (0x02)
Common header
Vendor ID 0x1022
Model ID 0x1202
Revision ID 0x00
PI 0x00
SubClass 0x00
BaseClass 0x06
Cache Line 0x00
Latency 0x00
Header 0x80
PCI header
Subvendor ID 0x0000
Subsystem ID 0x0000
Int. Line 0x00
Int. Pin 0x00
Dump
0 1 2 3 4 5 6 7 8 9 A B C D E F
00 22 10 02 12 00 00 00 00 00 00 00 06 00 00 80 00
10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40 01 00 00 00 81 00 00 00 00 00 00 00 00 00 00 00
50 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60 60 3F 38 00 00 00 00 00 00 00 00 00 00 00 00 00
70 00 00 00 00 00 00 00 00 05 00 80 0D 00 00 00 00
80 02 00 00 00 00 00 00 00 24 CA 6A 5D 34 03 12 00
90 10 00 01 00 0A 00 48 6F 20 00 00 80 4D 00 50 00
A0 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00
B0 E0 D0 CC 4F 2E 00 00 00 23 2F 8C C0 FD 1C 29 DC
C0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
D0 03 19 3C 14 09 C5 4F 90 05 68 92 AC 4E 6D 64 EA
E0 8E 49 11 9F 8E 71 2B 96 6C B3 DD 02 04 69 24 9D
F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

[tictac]

FELIX, let the BKDG help you ;) there's everything on setting correct values on DDR2-1066 and DDR3. I don't think that anyone wiil be able to send you such a dump soon. Don't forget, that only B stepping will be able to work with DDR2 at more than 667 (800\1066). Better read the datasheet, IMHO.
It doesn't work with all of the 9xx - thats the matter of fact ;) so this is why I ask. Can the check be bypassed? I'll wait, but if you need some help with the docs... ;)
STEvil 5000X has PCI registers, so can be tweaked by WPCREDIT using the datasheet (it's available). But you can't change the timings by software though ;) We've had a lot of discussion on Overclockers.ru forum on this theme.

Low level memory tyiming programming


macro MTT2 0,1,2 ; For AMD Socket F (Set both memory Controller with same timing)
{ ; 0=address; 1=data set; 2=data location
mov eax,0 ; copy register address
mov ebx,1 ; copy register data
mov dx,address ; set port address
out dx,eax ; send address through the port
mov dx,data ; set port data
in eax,dx ; Receive data
and eax,2 ; set data in eax
or eax,ebx ; increase data
mov ebx,eax ; copy memory timing to ebx stack
out dx,eax ; send timing to memory controller 1
mov eax,0 ; copy register address
or eax,000000800h ; set timing to memory controller 2 address
mov dx,address ; set port address
out dx,eax ; send address through the port
mov dx,data ; set port data
mov eax,ebx ; copy memory timing to eax
out dx,eax ; send timing to memory controller 2
}

[mongoled]

This is why i love XS so much

I don't think that anyone wiil be able to send you such a dump soon.
a few posts later.....

Phenom X4 dump
:p:

everyone working to helping the community

:up:

[Antinomy]

tictac
Phenom X4 dump:eek:
Not good in programming though :( especially in ASM.
mongoled,
everyone working to helping the communityAnd that's great! :)