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alpha754293
06-12-2006, 11:36 AM
Anyone know the FLOP count of Intel's latest?

Fuji
06-12-2006, 01:47 PM
flop as in FPU? I heard around 38ish.

http://www.theinquirer.net/?article=31836

freecableguy
06-12-2006, 01:53 PM
If this doesn't impress I don't know what will...quick run at 3.87Ghz (9x430):


http://members.cox.net/kjboughton/3.87_arth.JPG


http://members.cox.net/kjboughton/3.87_mm.JPG


-FCG

accord99
06-12-2006, 02:13 PM
8 single-precision per cycle per core
4 double-precision per cycle per core

[cTx]Philosophy
06-12-2006, 02:26 PM
Good lord FCG, thats most impressive..

alpha754293
06-16-2006, 06:26 PM
If this doesn't impress I don't know what will...quick run at 3.87Ghz (9x430):


http://members.cox.net/kjboughton/3.87_arth.JPG


http://members.cox.net/kjboughton/3.87_mm.JPG


-FCG

(dang though....24.5 GFLOPS - wow!)

Can you also download one of the older releases for Sandra because I think that the algorithm that they're using to get those values are different than what they have done in the past?

For example, my Mobile Athlon 64 3000+ was 2820 core FPU, 3650 with SSE2 extensions using I think it was Sandra 2005 (I don't remember which one.)

The new one is reporting 3819 core FPU, 5202 iSSE2 (MFLOPS). There is NO freaking way that my processor suddenly gained between 35.4-45.2% in FLOP, ESPECIALLY given that I have a fair number of things that are running in the background.

And this is stock - it's on my laptop, so I don't really much in way of a choice to overclock it.

Makes you kind of wonder eh?

And I KNOW that from the previous releases that the result were far more reliable than the current release.

*edit*

Could you disable SSE2 and SSE3 in the benchmark? (so looking at strictly core FPU only)?


*edit*

I just rebenched my craptop with Sandra 2005 SR3 (downloaded from Guru3D.com) and I got 2815 core FPU and 3626 iSSE2 (MFLOPS).

savantu
06-16-2006, 11:18 PM
An K8 can do 2 FLOPS/cycle , P4 the same .

970PPC , Itanium , Power 5 , K8L , Conroe do 4 FLOPS/cycle ( some do it with FMACs some with SIMD )

So a Conroe has a FLOPS rating of freq*4 FLOPS*2 cores.

For a 3GHz Conroe you have 3000*4*2=24 GFLOPS.

Fuji
06-17-2006, 02:22 PM
it's it 6? Conroe is supposed to have 3 128 bit single clock SSE2 FPUs.

alpha754293
06-17-2006, 05:12 PM
An K8 can do 2 FLOPS/cycle , P4 the same .

970PPC , Itanium , Power 5 , K8L , Conroe do 4 FLOPS/cycle ( some do it with FMACs some with SIMD )

So a Conroe has a FLOPS rating of freq*4 FLOPS*2 cores.

For a 3GHz Conroe you have 3000*4*2=24 GFLOPS.

Not for core FPU.

Core FPU for K7/K8 series (IIRC) is between 1.45-1.6 FLOPS/cycle.

For P4 (I don't know about the current generation) but historically, it's been closer to 0.55-0.6 FLOPS/cycle.

I typically only go by core FPU measurements because it is regardless of any extensions and implementation of such. (i.e. ever wonder why 3DNow! is never used to for FLOP calculations, but SSE are? Despite compilers being able to optimize for both? (neglecting marketing, and/or business aspects - only looking at it from the technical point of view).

POWER5 is 4 FLOP/cycle. PPC isn't. (I think they're around 2.8). Itanium isn't. Itanium2 is. (but that's also because from a structure/architecture perspective, it is VERY VERY VERY similar to the POWER, and I'd go so far to say that it is modelled after it given the original Itanium was a totally flunk.)

savantu
06-18-2006, 02:02 AM
Huh ? Comparing apples and oranges.

I'm talking theoretical maximum not real world.

Btw, 970PPC is capable of 4 DP FLOPS.

As for Itanium , I meant Itanium 2 since IMO Merced was nothing more than a flop/test.I think you should reconsider your coments about Itanium 2's ISA/implementation because it is anything but similar to Power . ( EPIC vs. RISC .... )

alpha754293
06-18-2006, 07:21 AM
Huh ? Comparing apples and oranges.

I'm talking theoretical maximum not real world.

Btw, 970PPC is capable of 4 DP FLOPS.

As for Itanium , I meant Itanium 2 since IMO Merced was nothing more than a flop/test.I think you should reconsider your coments about Itanium 2's ISA/implementation because it is anything but similar to Power . ( EPIC vs. RISC .... )

See the similarities in the block diagram between the POWER4 core and the Itanium2 core:

http://www.top500.org/orsc/2004/power4.html#power4

http://www.top500.org/orsc/2005/itanium.html#itanium

You might be right, about the PowerPC 970 capable of doing 4 FLOPS/cycle. I stand corrected.

As far as I know, POWER (including PowerPC) and Itanium2 are the only processors that I know of commercially that can do 4 FLOPS/cycle. Gee...I wonder why that is. (Because up until the introduction of the Itanium2, POWERs were the only ones capable of doing so, that were commerically available).

(Note/Disclaimer: I exclude Crays from the "commerically available" list because there are a fair number of restrictions from various government agencies on owning/using one - both in the U.S. and Canada.)