AMD shows off details of K8L

[StyM]

source (http://www.theinquirer.net/?article=31761)

N HIS KEYNOTE, Chuck Moore basically laid out the K8L in slightly more detail than we did. Either way, here are the highlights.

First, it has a shared expandable L3 cache, necessary because it is a native quad-core design. The one massive enhancement to the mix is that AMD finally has the ability to independently change core voltages for power savings. It now can also change the north bridge voltage independently of the cores. This is a huge win, we are told voltage differentials and problems with them were one of the main scaling headaches of the K8 core to this point.

Next is memory. The new core will support 48-bit addressing and 1GB pages. Cray and SGI will be very happy with this, until they hit that memory wall again. There is also official co-processor support, strongly hinted to be on a HTX card. The key here will be the platform is aware of them vs having to hack them in.

The other whopper Chuck dropped was that DDR2 is coming and DDR3 is in the wings when the spec 'settles down'. Old news, FB-DIMMs are the future, right? AMD has said they are supporting them, but the big news is that they are not forcing support. Unlike Intel's approach, Blackford supports only FBD, AMD will let you choose. This seems to strongly suggest that the controller on the later gens will be quite flexible indeed.

Next up is RAS, another area where AMD is sorely lacking. It is addressing the major sore points with support for memory mirroring, data poisoning support, and HT retry. It looks like it is following the IBM roadmap more than the Intel one here.

IPC is also going up in a big way. It is doing the obvious doubling of SSE/FP resources, old news now, but it goes a lot deeper than that. There are a bunch of added instructions, starting with the bit manipulation instructions LZCNT and POPCNT. It also added SSE extensions EXTRQ/INSERTQ and MOVNTSD/MOVNTSS. No word on SSE4 though.

The last bit is much more aggressive prefetch to 'feed the beast'. It has gone from 16B to 32B, an obvious step with the added SSE number crunching power. On top of this, it has out of order loads, and other tweaks to use the available bandwidth in a much more efficient manner.

For those who thought K8L was more or less a tweaked K8, you are wrong. It looks like no part of the core has been left unmolested by the elves working the CAD stations. It looks like AMD will have a credible response to the Intel MCW architecture after all. 2007 will be a fight after all. µ

http://www.theinquirer.net/images/articles/K8L_die_shot.jpg


AMD readies hounds to blood Intel's next gen hares
source (http://www.theinquirer.net/?article=30042)

AMD IS NOT sitting on its hands in the face of the Intel Merom attack. It has the imminent Rev F cores coming, and after that, there is the somewhat mysterious K8L as it is mentioned, no doubt followed by others. If the current gen parts are Rev E, the next is Rev F, what is G and H, and when will they be out? E is 2005, F is 2006, so that would put G in 2007 and H in 2008.

We all know about F, code named Santa Rosa for the 2xx/8xx Opterons, and Santa Ana for the 1xx. They bring a new memory controller, DDR2-800, and all the long talked about goodies to the mix, and should be out at Computex. One thing it is not talking about on these beasties is enhanced memory RAS and quad-port crossbars.

AMD is not talking about releasing QC parts until G, but sources tell us if sales start flagging, or if Intel starts kicking them around, it could be pulled in to F this year. It is a marketing thing, just like DDR2 on E was, and of late, AMD seems to be very good at timing.

The parts are out there, and we are hearing various things, all centering around about a 10% performance gain, clock for clock. Server folks with 1207 parts tell us the gain is lower, desktop and gaming folks are aiming higher. It could just be variants among pre-release parts, or it could be the memory RAS taking a bite out of latency on the server parts. Either way, look for a bump.

So, what follows F? How about G? Names you say? 2xx/8xx is Deerhound and 1xx is also a hound, but no names yet, sorry. When? 2007, Q2/3 or so, which means they will be taping out any day now. They plug into 1207 and bring a lot to the table.

Everything I read tells me these will be quad core, and I have not seen a reference to a dually anywhere, but they no doubt will exist. The QC parts on 65nm are said to be about 250mm but I have not personally taken a ruler to one. This is a pretty impressive thing if you consider that it has a 2MB L3 cache, it looks like the F cache shrink will be carried over.

For features, it looks like G will drop all pretences of DDR1 and all of no one will stay up at night crying over it. In its place comes the next gen of Pacifica, basically almost full I/O virtualisation. We told you about the doubled FP units a bit ago, and they look to be 2x 64 not a widening to 128 bit. This should be one hell of a kick in the pants for the HPC set.

The HPC crowd will also love the memory controller enhancements. Think 1GB page tables and 48-bit physical addressing for a total of 256TB of RAM. Can you say Cray and SGI doing the happy dance? This part should have a happy home in large servers.

The problem for large Opteron machines is that they tend to suck at the 8S node, mainly because cache coherency traffic eats all of the HT bandwidth. If you want to fix this problem, you need to have a much better filtering system like that of Horus, which explains why AMD hired the guy who designed it. G will have just such an enhanced filter, but the reasons why, other than making 8-ways functional will have to wait for H.

Oh, H you say? Cerebus on 2xx/8xx and Wolfhound on 1xx? Yeah, they will go 16-way glueless, and it should actually not stink this time. Why? That is a long story, go get a drink and relax while you read. If you see references to AMD touting 64P systems, it is really this 16S 4C that they are talking about.

The first thing is that AMD will add a 6MB L3, but we have heard different numbers floating around. This will ease a lot of the pressure on the HT system, as will a boost to 2.6GHz. It looks like systems based on H will eat a huge chunk of the low end of the high end market or something like that. My head hurts from thinking about it.

The other big problem in this area is latency, AMD gets killed by the added latency of cache coherency when you go from 2S to 4S, and at 8S, goodnight Gracie. To handle this, you would need better topologies to reduce the number of hops seen by the traffic.

H addresses this in two ways. The most obvious is that they can do non-flat designs, IE diagonal links, and if they have a clue, and I think they do, hypercube configs. Here's to hoping. They also can split up HT links from 1x16 to 2x8, so if you need lower latency, you can trade peak bandwidth for it. This should make for some interesting routing layouts.

When you are talking boxes that big though, RAS is a topic that you can't avoid. AMD is not sitting still, and H will bring a huge raft of RAS enhancements. Instead of aping Intel, AMD is going to ape IBM. Nice target to pick for the market segment, but no specifics yet. The one thing that stands out looking at the Intel vs IBM RAS roadmaps is memory mirroring and RAID, but both sides will be there in 2008.

What are you going to feed this beast with? How about 4 FBD channels? Whether it is FBD 1 or 2 is still up in the air right now, but it will most likely be 2. AMD is down on FBD right now mainly because it has failed to live up to the power numbers, but latency also is not all that hot either. There is no choice to the decision in the end, but H looks like the longest they can possibly put it off.

There is a lot more in H, and it will come out sooner or later, as will all the details of G. F is all over the place, so there are few surprises still lurking in it. It looks like Intel will be back for late 2006 and early 2007, AMD for the following 12 months, and then the comes Neahlem vs Rev H battle. How that turns out is anyone's guess, but it sure will be fun to watch. Now that you know both sides, place your bets. µ

will it give core 2 a serious competition??

[Absolute_0]

Looks more competetive than i previously imagined, and they will need it :D

I like the way you can adjust voltage for every core -- hope that enters into the overclocking.

[3NZ0]

independant vcore is gonna be a hit with us lot :slobber:

im liking it...

[don_vercetti]

yeah, we can finally end those Core 0 weaker than core 1 things...just up core 0s voltage!

If AM2 clocks well this year (even the totally untweaked 90nm cpu's) and K8L is as good as it looks, it may yet be worth buying into AM2 (once DFI have a board, of course) rather than Conroe.

[r3w4]

They're always thinking of the enthusiasts. AMD, you had me at 'K8L.' :buddies:

[Cooper]

I see AMD already implemented Z-Ram tech into K8L - just look how less space does memory takes.

[oshua]

They're always thinking of the enthusiasts. AMD, you had me at 'K8L.' :buddies:
That and their server costumers.
Great news with all of these details.

[NiCKE^]

yeah, we can finally end those Core 0 weaker than core 1 things...just up core 0s voltage!

If AM2 clocks well this year (even the totally untweaked 90nm cpu's) and K8L is as good as it looks, it may yet be worth buying into AM2 (once DFI have a board, of course) rather than Conroe.
Conroe is going to kick ass :D

[metro.cl]

only one question how much for one of these???


it looks great on paper

[DilTech]

I knew AMD wasn't going to take Conroe lying down..

This could be a monster!

[Cybercat]

Conroe is going to kick ass :D no argument there. It will also be out sooner, but anyone worried or wondering how AMD is going to compete can rest easy. I'm really glad the K8L is more than a few tweaks.

[eBoy0]

Looks promising!
Cerebus, what a badass name!

[MaxxxRacer]

I knew that AMD wouldnt be sitting on its hands this round, and it looks like there will actually be a real fight ahead of us.

[Dimitriman]

I'm waiting for NNstep's comments :D... something on the lines of "I told you so..."

[R101]

K8L vs 45nm Conroes.. Great choices for us consumers :).

[NickS]

Oohh I cant WAIT to see results for this. This is going to be the real competition guys, get ready for both Intel & AMD to kick eachothers asses till the end. It's gonna be great. :D

Honestly, there can be cons too. If they're equally performing, ppl will be like, "OMG intel is WAAY better," or "OMG amd is WAYY better," when theres no *clear* winner. Oh well... we will see... we will see :evil:

Nick

[szukalski]

Looks like a lot of people may be able to retain their fanboy status..

[K404]

Intel do appear to have the best part of a year to help us forget about AMD though. Actually...if AMD reckon some of this could be implemented into AM2/S940, I hope Intel do very well and "force" AMD into bringing it forward- That could be a benefit. Intel stuff could never do that- new CPU? NEW MOBO.

If DDR3 could fit into 240-pin DIMM sockets, i`d be well happy. I think AMD will need more than 940 pins to implement quad-core though, unless i`ve not quite read that right.

Time will tell.

[Repoman]

I imagine if they do implement separate core voltage into overclocking, you would need a new board for that

[VulgarHandle]

so what is said is.. if sales are low, they'll bump up the release, hmmm, hate to say this, but, EVERYONE STOP BUYING AMD...for a while

[keiths]

He seems to say they go a lot deeper in increasing IPC, but adding instructions is, well, adding instructions, not improving IPC. The changes to keep the thing better feed should improve IPC. The doubling of floating point is also an IPC improvement but old news and only matches what Conroe does. L3 was also expected but they talk of it as recovering lost performance of added latency from increasing number of cores but there's a chance this will improve IPC past just recouping. The rest are non performance features for servers. The unknown that I've an open mind on is how much of a speed up the feeding improvments will give but it looks as expected and still, despite his insistance otherwise, more or less like a tweaked K8.

[Nanometer]

Oooo. A reason to stick with AMD. Sounds great to me, be impressive to see them deliver at speed.

[Fred_Pohl]

I'm confused about part of this news. IIRC AMD's latest official roadmap shows their first quad-cores launching in H1-08 and according to this story, K8L is a native quad-core. So is K8L launching in H1-08 like AMD says or in 2007 like The Inq says? Considering all the changes in K8L and it being supposedly a quad-core , I'd guess H1-08 is more likely but perhaps AMD will phase some of these changes into their dual-cores during 2007 or even move K8L up a quarter or two.

[Shadowmage]

I'm pretty sure that AMD will start shifting things around once Woodcrest et al. debuts...

[Repoman]

I'm confused about part of this news. IIRC AMD's latest official roadmap shows their first quad-cores launching in H1-08 and according to this story, K8L is a native quad-core. So is K8L launching in H1-08 like AMD says or in 2007 like The Inq says? Considering all the changes in K8L and it being supposedly a quad-core , I'd guess H1-08 is more likely but perhaps AMD will phase some of these changes into their dual-cores during 2007 or even move K8L up a quarter or two.

Quad core support. Just like K8 has dual core support, but old clawhammers certainly weren't dual core

[alexio]

250mm3 quad-core cpu's, I guess they will NEED voltage adjustment for each seperate core :rolleyes:

EDIT: Ofcourse because of scaling problems that would occur with such a large die.

[Shadowmage]

That's for the servers... I wouldn't be surprised if half of those features weren't supported on the desktop versions.

[Revv23]

I see AMD already implemented Z-Ram tech into K8L - just look how less space does memory takes.


Good Catch!!!

That is one tiny little cache!

[alexio]

Good Catch!!!

That is one tiny little cache!

And one slow cache. I think it would still need a faster L2 cache besides it. Maybe they can make the cpu as fast but smaller using this tech by making the L2 cache very small and the L3 cache much larger in kb with this tech.

[Carfax]

If the FPUs are 2x64, then I doubt the K8L will have the 1 cycle throughput that Merom and Conroe has.

But I may be wrong.

[Shadowmage]

That may be true, but then K8L will have nearly double the FPUs as that of NGMA. It'll also have one more SSE unit than the NGMA.

[situman]

Nice, AMD effectively killed most early AM2 sales. I know I will be sitting on my hands and wallets and see what K8L offers before I switch platforms.

[nn_step]

Mmmmm DDR3 :D

[Repoman]

And one slow cache. I think it would still need a faster L2 cache besides it. Maybe they can make the cpu as fast but smaller using this tech by making the L2 cache very small and the L3 cache much larger in kb with this tech.

How slow is it :stick: I imagine AMD would make it quite a bit faster than the DDR2/3 RAM or it's not even worth having it on there

[MaxxxRacer]

How slow is it :stick: I imagine AMD would make it quite a bit faster than the DDR2/3 RAM or it's not even worth having it on there

As far as the latest data (that I have read anyway) on Z-Ram is concerned it is slower than conventional L2 Cache.

[nn_step]

As far as the latest data (that I have read anyway) on Z-Ram is concerned it is slower than conventional L2 Cache.
Only when the capacity is below 2Mb ;) the larger the Cache the faster it is compared to traditional Cache

[Repoman]

As far as the latest data (that I have read anyway) on Z-Ram is concerned it is slower than conventional L2 Cache.

I figured that, only makes sense that L3 cache will be slower than L2. L1>L2>L3, but you can only have so much the fastest levels.. imagine 4MB of ~23GB/s L1, no need for anything else

[kl0012]

That may be true, but then K8L will have nearly double the FPUs as that of NGMA. It'll also have one more SSE unit than the NGMA.

It has 2x128 bit SSE units (ADD+MUL) and can handle up to 4 DP FLOPS/cycle. Conroe can do exactly the same thing.
http://news.com.com//i/ne/p/2006/amdslide4_532x402.jpg

[nn_step]

Don't you love the Irony.. I was saying DDR3 and was getting ripped upon by it because of AMD slides yet now AMD slides seem to agree with me after all.. :p:

[Bar81]

Nice, AMD effectively killed most early AM2 sales. I know I will be sitting on my hands and wallets and see what K8L offers before I switch platforms.

The smart people were already doing this :p:

[alexio]

Don't you love the Irony.. I was saying DDR3 and was getting ripped upon by it because of AMD slides yet now AMD slides seem to agree with me after all.. :p:

You said AM2 would use DDR3 right? This is not quite AM2, this is K8L and will follow after AM2.

[Bar81]

Don't you love the Irony.. I was saying DDR3 and was getting ripped upon by it because of AMD slides yet now AMD slides seem to agree with me after all.. :p:

Keep on playing in your little dream world. You got ripped because you were pulling things out of your uninformed ass. Oh gee, you're such a genius for predicting that after DDR2, AMD would be going to....wait for it....almost there...DDR3!!!

You just don't know when to stop embarassing yourself. You're clueless.

[nn_step]

You said AM2 would use DDR3 right? This is not quite AM2, this is K8L and will follow after AM2.
M2, AM2 is something a little bit different ;)

[situman]

The smart people were already doing this :p:

Some smart people sometimes needs a little more persuasion

[Bar81]

Some smart people sometimes needs a little more persuasion

Fair enough :D

[hipro5]

Oohh I cant WAIT to see results for this. This is going to be the real competition guys, get ready for both Intel & AMD to kick eachothers asses till the end. It's gonna be great. :D

Honestly, there can be cons too. If they're equally performing, ppl will be like, "OMG intel is WAAY better," or "OMG amd is WAYY better," when theres no *clear* winner. Oh well... we will see... we will see :evil:

Nick

IF they both do perform quit well, there are some questions.....Is AMD going to drop prices so as to be competitive?....coz if not, they will lose the game......;) .....Are the AMD's new CPUs NOT going to have a cold bug problem?.....coz if they DO have a cold bug problem and Conroe don't, they'll lose as overclockers.....;)

[MaxxxRacer]

I think the cold bug question is a long dead one. After discovering the reasons for the cold bug, it seems likely that they will not be fixed in later iterations of AMD CPU's unless there is a HUGE redesign of the entire arhcitecture.

BUT I could be wrong.. (kind of hope that I am)

[Vapor]

If nV could patch up G70-256's coldbug (bugged for very similar reasons) for the G70-512 and G71, I'd bet AMD can do it. Whether or not they will is another story. I would really love to see non-CB'd AMD chips and have real competition at the top for a sustained time. The CB is damn annoying on a few levels (not that I've ever run into a problem with the coldbug (even with DICE, lol)).

[NinjaWreck]

Keep on playing in your little dream world. You got ripped because you were pulling things out of your uninformed ass. Oh gee, you're such a genius for predicting that after DDR2, AMD would be going to....wait for it....almost there...DDR3!!!

You just don't know when to stop embarassing yourself. You're clueless.

Can we please get off of this argument? It seems every AMD thread leads to an nn_step bashing. Does it really matter if he's BSing people or not? It's not like he's giving up any useful information.

[DilTech]

He seems to say they go a lot deeper in increasing IPC, but adding instructions is, well, adding instructions, not improving IPC. The changes to keep the thing better feed should improve IPC. The doubling of floating point is also an IPC improvement but old news and only matches what Conroe does. L3 was also expected but they talk of it as recovering lost performance of added latency from increasing number of cores but there's a chance this will improve IPC past just recouping. The rest are non performance features for servers. The unknown that I've an open mind on is how much of a speed up the feeding improvments will give but it looks as expected and still, despite his insistance otherwise, more or less like a tweaked K8.

Floating point is conroes weakness, Int is conroes strong point. Doubling the FPU on K8L will allow it to MAUL conroe in floating point calculations, they won't even be on the same page.

Also, if it's more efficient at those extensions, like it should be, that would allow it to do them in less cycles, which would increase the IPC, no?


I think the cold bug question is a long dead one. After discovering the reasons for the cold bug, it seems likely that they will not be fixed in later iterations of AMD CPU's unless there is a HUGE redesign of the entire arhcitecture.

BUT I could be wrong.. (kind of hope that I am)

Actually.... Am I wrong in thinking that 130nm A64's didn't have the cold bug? If I'm not mistaken(I could be as I don't do sub-zero) it wasn't until winchester that the cold bug showed it's ugly head... If that's the case, there's a 50/50(130nm didn't vs 90nm did) chance that A64's at 65nm won't have the bug, right?

[accord99]

Floating point is conroes weakness, Int is conroes strong point. Doubling the FPU on K8L will allow it to MAUL conroe in floating point calculations, they won't even be on the same page.
The K8L didn't double the FPUs, they extended it to 128-bit, just like Conroe. Both have the exact same capabilities, 4 DP/cycle.

[Entity_Razer]

Keep on playing in your little dream world. You got ripped because you were pulling things out of your uninformed ass. Oh gee, you're such a genius for predicting that after DDR2, AMD would be going to....wait for it....almost there...DDR3!!!

You just don't know when to stop embarassing yourself. You're clueless.

May I advice you to tone it down a bit and not to flame people in the forums? Manners like this WILL results in a warning/vacation if you keep it up so think it, but don't say it or PM your opinion to him. NOT in the open fora. Got it?

Now on the k8l, it's good to see AMD came up with a nice answer :) I don't think conroe is Quad Core by nature so this gives AMD another edge and they'll be able to produce Quad cores faster then intel because intell will need to roll out a new design etc, while AMD just needs to change the computers that run their plants, do some testruns and if it goes well just let it go with the flow :)

[Bar81]

May I advice you to tone it down a bit and not to flame people in the forums? Manners like this WILL results in a warning/vacation if you keep it up so think it, but don't say it or PM your opinion to him. NOT in the open fora. Got it?



My advice is to mind your own business.

[biohead]

My advice is to mind your own business.
Actually, smartass, this IS his business. See his bold name?

[Revv23]

If nV could patch up G70-256's coldbug (bugged for very similar reasons) for the G70-512 and G71, I'd bet AMD can do it. Whether or not they will is another story. I would really love to see non-CB'd AMD chips and have real competition at the top for a sustained time. The CB is damn annoying on a few levels (not that I've ever run into a problem with the coldbug (even with DICE, lol)).

well we know they can, otherwise there wouldnt be 90nm chips out there without the bug.

[Revv23]

Now on the k8l, it's good to see AMD came up with a nice answer :) I don't think conroe is Quad Core by nature so this gives AMD another edge and they'll be able to produce Quad cores faster then intel because intell will need to roll out a new design etc, while AMD just needs to change the computers that run their plants, do some testruns and if it goes well just let it go with the flow :)


Correct, conroe is not quad core, but intel is planning on doing the same thing they did with the P-D line by just bridging the chips together.

This saved intel alot on yeilds last time around and it will this time.

Think about it, AMD gets a quad core chip with 1 bad core, they now sell it as a dual core. Intel gets a chips with 1 bad core, they sell a single core and a dual core.

[nn_step]

Correct, conroe is not quad core, but intel is planning on doing the same thing they did with the P-D line by just bridging the chips together.

This saved intel alot on yeilds last time around and it will this time.

Think about it, AMD gets a quad core chip with 1 bad core, they now sell it as a dual core. Intel gets a chips with 1 bad core, they sell a single core and a dual core.
True but do to the FSB limitations that currently exist on s775 boards.. it is going to strangle performance.
One might think they might sell Triple core Procs if enough Single core defective Dies start showing up :D

[Cooper]

http://img181.imageshack.us/img181/486/quadcoreroadmappkmo6rh8gnt16mu.jpg

[Bar81]

Actually, smartass, this IS his business. See his bold name?

Thanks for the revelation of the obvious. I was already "advised" by another admin and we hashed it out. No need to beat a dead horse.

[onewingedangel]

Correct, conroe is not quad core, but intel is planning on doing the same thing they did with the P-D line by just bridging the chips together.

This saved intel alot on yeilds last time around and it will this time.

Think about it, AMD gets a quad core chip with 1 bad core, they now sell it as a dual core. Intel gets a chips with 1 bad core, they sell a single core and a dual core.

Acyually they're forced to sell one die as a single core the dual core die can go towards either a dual or quad core part, so theres actually even more flexibility for intel, if quad cores aren't selling well the dies can be sold in dual core form, and if there's excess demand for quad cores, dual cores can be packages as quads. It makes a great deal of sense for intel to scale cores this way.

In regards to the fsb bus problem, I assume they will go with the 3 stage cache approach, with each core having its own l1, sharing l2 with the other on die core, and a l3 cache being shared between the two dies. Plus I believe conroe contains logic to allow it to communicate with another die over a dedicated pathway, rather than having to go over the fsb, which should cut out a lot of fsb traffic in a mcm approach.

[3NZ0]

Thanks for the revelation of the obvious. I was already "advised" by another admin and we hashed it out. No need to beat a dead horse.

oh!
i want to beat the dead horse! ;)


:horse:



:D

does anyone know when intel will move to an intergrated nb like amd?

[Fred_Pohl]

Quad core support. Just like K8 has dual core support, but old clawhammers certainly weren't dual core

Any chance that K8L might reach the desktop before H1-08? I've seen some speculation that Brisbane might include some K8L features but lately all the sources I've seen are saying that Brisbane is just a 65nm K8 with improved sSOI, SMT and VT.

[Fred_Pohl]

Plus I believe conroe contains logic to allow it to communicate with another die over a dedicated pathway, rather than having to go over the fsb, which should cut out a lot of fsb traffic in a mcm approach.

It does. Core 2 was designed from the start as a multi-core cpu intended to scale to at least 8 cores.

[The Ghost]

I'm confused about part of this news. IIRC AMD's latest official roadmap shows their first quad-cores launching in H1-08 and according to this story, K8L is a native quad-core. So is K8L launching in H1-08 like AMD says or in 2007 like The Inq says? Considering all the changes in K8L and it being supposedly a quad-core , I'd guess H1-08 is more likely but perhaps AMD will phase some of these changes into their dual-cores during 2007 or even move K8L up a quarter or two.
a picture is worth how many words ?
http://img.photobucket.com/albums/v101/theghost1/brisbane.jpg

[The Ghost]

It does. Core 2 was designed from the start as a multi-core cpu intended to scale to at least 8 cores.
not with out a working CSI or AMD's hypertransport

[VulgarHandle]

am2, k8l, f, all will still run on the 200 standard, right? i.e. 200x12=2400, 1:2 w/ ddr2(am2 4800+), right?

if you were to run 400x6 1:1 w/ ddr2 would it show an improvement?

[Absolute_0]

I was under the impression AM2 would be changing the 200 base on at least some chips, i saw mentions of 2.66 clock speeds, did AMD dump that?

[Cooper]

AMD will move to 266 or maybe even 333 just to make RAM frequency dividers with less losses ;)

[VulgarHandle]

I was under the impression AM2 would be changing the 200 base on at least some chips, i saw mentions of 2.66 clock speeds, did AMD dump that?

see, that's what i thought too...
http://www.c627627.com/AMD/Athlon64/

but i've seen some screens that show otherwise..
http://www.xtremesystems.org/forums/showthread.php?t=99429

i've had another discussion somewhere else, but i can't seem to find it, but i was told it was still the 200 standard

[ORCBEAST]

Correct, conroe is not quad core, but intel is planning on doing the same thing they did with the P-D line by just bridging the chips together.

This saved intel alot on yeilds last time around and it will this time.

Think about it, AMD gets a quad core chip with 1 bad core, they now sell it as a dual core. Intel gets a chips with 1 bad core, they sell a single core and a dual core.

From what I have heard and read Intel will have Kentsfield in Q1 07 but will be very FSB starved. Then round about AMD releases theres, Intel will release a CPU called Bloomsfield which each core will have its own FSB or maybe even onboard MC...I dont know much but good luck to both.

<img src="http://66.49.136.31/many/ani_smiley_flog_dead_horse.gif">

[zakelwe]

I thought the quad Intel cores had two FSB's .. DIBS or something ?! My memory is going ( maybe like Intels :) ) .

Looks like a tough battle on the server front anyway.

Regards

Andy

[onewingedangel]

DIB refers to each socket getting its own fsb, so two xeon dp/mp's don't have to share the same fsb, I don't believe it applies to MCM where only one socket is used.

[DilTech]

It does. Core 2 was designed from the start as a multi-core cpu intended to scale to at least 8 cores.

Wrong... It was built as a native dual core. Quad will be done like the presler, atleast their first gen quad-core will. CSI was canned awhile ago, and intel was too stupid to sign on for HTT when AMD offered as it is a joint technology between a few companies.
:slapass:

[onewingedangel]

I believe that the cores on a die communicate amongst themselves with direct cache to cache access, but theres also a pathway for interdie communications other than the fsb. I remember reading this a while ago. With this in place it would mean scaling up to 8 cores (2x 4 core dies) which will then be followed by the CSI enabled chips.

[StyM]

AMD's Spring Forum just finished up and industry insiders got a chance to sit down with DailyTech and discuss the major cornerstone of the forum, K8L. K8L is AMD's next generation processor technology, which Henri Richard first revealed to Chris Hall at Digitimes back in March. Richard himself described K8L as evolutionary, rather than revolutionary, and it appears as though that comment was spot on the mark from the details of K8L we've seen.

Chuck Moore, a senior AMD Fellow, gave a presentation at AMD's Spring Forum revealing some of K8L's features. Aside from being a quad-core-friendly architecture, there are three key features that will separate K8L from K8: cache, memory and HyperTransport.

Moore revealed that K8L will be the first AMD processor to have L3 cache since the K6 CPU. Each core has an independent L2 cache, but the entire processor shares an L3 cache pool. There's no word yet on exactly how much cache the K8L can hold, though the K8L will be a 65nm SOI process so AMD engineers have a bit more die real estate to play around with.

K8L will support DDR2 and DDR3 when it becomes available, although it’s still anyone's guess as to whether or not the market will actually adopt DDR3 quickly enough to warrant using DDR3 aggressively at the core launch. Tom Trill, Samsung's Director of DRAM Marketing, was extremely hesitant to claim DDR3 would make it to the desktop without "significant" performance gains over DDR2 -- lest anyone repeat many of the mistakes made when the industry migrated from DDR1 to DDR2.

HyperTransport 3 will be a key element of K8L. HyperTransport 3, which was just ratified a few weeks ago, increases the frequency of the current HyperTransport bus from 1.4GHz to 2.6GHz, or from 2.8GT/s to 5.2GT/s. Current AMD Opteron processors only support HT links operating at 1GHz, though the HT 2.0 specification allows these links to run as fast as 1.4GHz. Non-K8 quad core processors will almost certainly take advantage of this additional headroom as data across these links gets more crowded. However, K8L processors will have the advantage of using the full 5.2GT/s per link defined in HyperTransport 3.

K8L processors are expected to be very co-processor friendly, allowing for additional HT and HTX interconnects specifically for math or cryptography acceleration. Current Opteron 2xx and 8xx processors use three HyperTransport links per die, but AMD's documentation did not reveal how many HyperTransport links K8L would utilize. Recently, AMD's Phil Hester claimed embedded on-chip coprocessors were part of the company's long term plan just a few months ago. While we may not see embedded co-processors with the K8L, it does look like the architecture is gearing towards supporting co-processors in a big way.

Behind closed doors, insiders revealed to DailyTech a few tidbits of the long term quad core roadmap. AMD will introduce no less than four quad-core families over the next two years, with the first being Deerhound. Deerhound, we are told, will be a Socket F server processor expected to ship late next year on the K8 -- not K8L -- architecture. Deerhound did not appear to support FB-DIMM.

In early 2008, AMD's corporate roadmap claims a quad core desktop CPU will make an appearance, dubbed Greyhound. Greyhound is slated to become the first quad-core AMD chip to use the HyperTransport 3 bus, and the memory controller is slated to support DDR2 and DDR3. Unlike Deerhound, Greyhound will use the K8L architecture, and all the goodies that come with it, including the 5.2GT/s HyperTransport support. Unless AMD's plans change drastically between now and 2008, the processors will require a new socket.

There are very few details of the other two processor families, but hopefully future forums will get a chance to touch on some of those developments as they firm up. However, we do know that server processor cores are expected to migrate to K8L after Deerhound.

K8L has a few other highlights, including dynamic powering of sections of the processor -- a page taken straight out of Intel's Yonah playbook. The p-states, as far as we can tell, will be separate for each core and the memory controller. The K8L core will also have a 32-bit prefetch (versus 16 right now), 48-bit addressing with 1GB pages and the ability to process 128-bit SSE instructions in a single cycle, another very Intel-esque feature.

Expect to see more tidbits over the next few days as roadmaps and transcripts are still being released.

source (http://www.dailytech.com/article.aspx?newsid=2388)