FX to have L3?

[Otaking71]

http://www.theinquirer.net/?article=29738

[nn_step]

Well if it is true.. think an extra 40watts of heat

[Sentential]

Bogus if you ask me. :nono: :fact:

[[XC] Lead Head]

I heard AMD bought some technology to allow them to have 4MB Cache or something like that withing reasonable heat levels

[nn_step]

I heard AMD bought some technology to allow them to have 4MB Cache or something like that withing reasonable heat levels
Yes it is called Z-ram but it would just double the cache size... without increasing the heat production...4Mb of L3 would still increase it by 40w

[freecableguy]

Yes it is called Z-ram but it would just double the cache size... without increasing the heat production...4Mb of L3 would still increase it by 40w

where you guys get these numbers is beyond me. even extremely high speed GDDR3 (which can be as much as 64MB per chip) only consumes 3-5W. 40W? try again... :slap:

[Starscream]

did read that they are gone use alot fo new optimisations in the AM2 wich will lower the power usage for the new CPUs.

[metro.cl]

where you guys get these numbers is beyond me. even extremely high speed GDDR3 (which can be as much as 64MB per chip) only consumes 3-5W. 40W? try again... :slap:


so how much will 4mb of l3 cache consume??

[[XC] moddolicous]

In all fairness, I think that cache is faster then gddr3 memory. How much does L3 cache really make in a chip. I know L2 cache make a difference (IE 512kb vs 1mb) but will 4mb L3 cache make a difference?

[Der_KHAN]

hmm, what was the last intel/amd cpu that had an l3 cache?

[coldpower27]

hmm, what was the last intel/amd cpu that had an l3 cache?

Intel Side
On Desktop?

Pentium 4 Extreme Edition 3.46GHZ/1066FSB/512KB LV2/2MB LV3

On Server?

Xeon Server MP's always have some form of LV3 cache, for the top end models.
Potomac-8MB 3.3GHZ/667FSB/1MB LV2/8MB LV3
Tulsa-16MB 3.xGHZ/800FSB/2x1MB LV2/16MB LV3 Shared (Soon not yet)

AMD Side

Never in the life of K7 or K8 has AMD had LV3 cache to my knowledge...

[[XC] leviathan18]

qafaik lvl 3 cache is due to 2007

[mursaat]

At what speeds do the Intel L3 run? Is it much cheaper to have 4Mb L3 than 2Mb L2 per core?

[Zyklon5]

AM2 dual core will be divided into 4 TDP categories:

35w for the 3800+ dual core launching Q2'06
65w for the 3800+/4800+ dual core launching Q2'06 through Q3'06
85w/89w i've seen both figures around for the 3800+/4800+ dual core
125w for the FX-62

So there will be quite a diference in power between the normal and FX line of CPU's, it would be nice if it came from that 4MB L3 cache .. maybe the FX would have the same core as a 2xx or 8xx L3 enabled Opteron.

http://www.dailytech.com/article.aspx?newsid=850
http://www.hkepc.com/bbs/viewthread.php?tid=550178&extra=page%3D1

[eddieate]

It doesn't really matter that the FX will be really hot does it?
I mean most people with FX's run them on phase units and with the current coldbug situation a bit more heat could be a good thing.
/Ed

[onewingedangel]

I'm not sure if l3 will really help amd though, intels uses it to compensate for lacklustre I/O, AMD's I/O is already excellent and as such I think we would see far less performance increase due to l3. l3 cache will certainly be beneficial when we are talking about multi chip modules though, which allows far better yields due to simpler cores, and yet takes a negligable performance hit as the l3 cache will make up for the hit in io bandwidth.

[DeltZ]

ok...my noob question of the day.....
what is the difference between Level 1 Level 2 and Level 3 cache?

[onewingedangel]

level one is a small extremely fast cache that holds the instructions that are to be fed into the cpu pipeline. l2 is usually half the speed or less of the l1, but is many times larger, and contains both instructions that are to be fed into the pipeline, as well as data that may be required or is being continuously fed in and out of l1. l3 cache serves much the same purpose as l2, and provides more space for data to be held, it is however far slower than l2 again. The main memory feeds the large l3 which feeds the smaller but faster l2, which in turn feeds the smaller and faster l1.

So if you have 8MB l3 you have 8Mb of data stored in a faster than main memory store that the cpu can work with, with the data most likely to be worked on being prioritised and stored in l2, and the instructions to be fed into the cpu stored in l1. Where possible an increase in l2 is preferable to adding l3 as it is much faster and increases the workable data ammount, as the contents of l1 and l2 have to be stored in l3, so you effectively have the size of the lowest level cache, but with faster smaller stores. Increasing l2 gives you more room at a higher speed - this is why a cpu with 2Mb L2 would be preferable to a cpu with 1MB l2 and 2MB l3. However issues with latency when increasing cache sizes beyond certain limits (as well as increasing the likelihood of defects) means that level 2 cache can only be grown so far before you see diminishing returns and this is where l3 cache comes in handy.

Most modern l3 is off die but on chip (a daughter die if you wish), which allows existing cpu designs to have l3 cache added without taping out a new design (eg. mp xeons are a prescott or smithfield core with mp support and added l3) and also increases yields. This is often used in multi-processor xeons to compensate for the lower front side bus speeds, as having a larger local store helps compensate for the slower access to the main store of data held in main memory.

[mursaat]

Really good explanation. Some intros would help tho :p

So my question. What is better, "64kb L1 + 2Mb L2" or 64Kb L1 + "1MbL2 + 4Mb L3" (all that per core)? If there's a clear winner, is cheaper or more expensive?

[onewingedangel]

Really good explanation. Some intros would help tho :p

So my question. What is better, "64kb L1 + 2Mb L2" or 64Kb L1 + "1MbL2 + 4Mb L3" (all that per core)? If there's a clear winner, is cheaper or more expensive?

In that example it would depend on what type of data you were processing. If you were accessing less than 2MB at a time the first example would be better, yet if you were accessing more than 2MB at a time the second example would be better. Also if you have a slower front side bus the larger albeit slower l3 cache would likely help you more than the larger l2, but again it totally depends on the workloads involved.

Adding l3 cache is a cheaper alternative for AMD as it likely doesn't involve taping out new dies, as l3 cache can be added on module, rather than on die, however increasing the l2 size would have likely netted a greater performance increase due to the a64s already excellent io design. For dual cores it may benefit somewhat in the short term, as AMd still doesn't have shared l2, but hopefully this shortcoming will be sorted before long. Ideally you would have l1 per core, shared l2 per die, and shared l3 per module.

[DeltZ]

so what's the absolute limit for size of Level 1? What technical difficulties occur when making level 1 larger....specifically...not just yield numbers.

[onewingedangel]

L1 caches are specific to the architectures involved, you cant just up the level 1 cache sizes in the way you can level 2 caches - level one caches are very specific in what they hold and where they feed the data - it is just the place the data goes immediately before it its fed into the cpu pipeline, its not for storing speculative data like l2 and l3 is.

Pentium 4's have a complex l1 cache design which if I remember correctly totals 64kb, and the a64 has a fixed 128kb l1 cache, this is not to say that the a64 has better l1 cache, as these are simply the ammounts of l1 cache the architectures use.

edit:wikipedia suggests the p4s actually have only 20/28kb of l1 cache, made up of a 8kb(32bit p4's)/16 KB(64bit p4's) L1 data and a 12 KB L1 instruction cache, which just exagerates the point I made above.

[freecableguy]

L1 > L2 > L3
usually L1 maps to L2 which maps to L3. this means that the total amount of cache available is really sizeof(L3) with L1 and L2 being smaller subsets so that their data rows and columns being contained entirely within the larger L3 mapping. there are two reasons for this:

1) processor design in that small data sets are usually accessed faster with lower latencies as it is "faster" to address smaller data sets since there is less address decoding necessary. example: why refer to your state (where you live) when everyone lives in the same state. see where i'm getting at here? (btw, this is dumbed down for extreme clarity).

2) LATENCY! "simpler" cache designs have lower latencies = higher BW and efficiency = higher performance = :)

While L2 may be better than L3, the fact of the matter is that the 'San Diego' cores aren't designed to address more than 1MB of L2 cache. Hence the limitation. A major core revision (ref F???? heh) is required to address this (get it? get it? ha, i'm so witty).

-FCG

[DeltZ]

thank you for the replies :) I am enlightened :woot:

[Lightman]

Everything what say onewingedangel is almost true, but he forget that AMD uses exclusive cache structure (inclusive on Intel side), so it means that data from L1 cache isn't stored in L2 at the same time, and this give 1152KB of usable cache for Opteron family, and it may give 5248KB cache for new FX-62 if L3 will be still exclusive ;)

Time will tell:D

PS. L3 cache will give some good preformance boost on server side in most games and in threaded aplications, but not in 3d animation software, math programs or encoding software

[[XC] Lead Head]

AFAIK the only AMDs with L3 cache to date were the K6-2+ and the K6-3

[nn_step]

pff i would be glad ig they released a 2MB chip with latencies of 10ns (vs 1Mb 17ns a64):D
By you also have to remember that L2 Cache latency has a bit to do with your ablity to overclock
http://www.adriansrojakpot.com/Speed_Demonz/L2_Cache_Latency/L2_Cache_Latency_03.htm
Now a Bios option to adjust it would be nice....

[Pinnacle]

Does anyone here have any idea how much 1 meg of L1 cache costs to produce?

[nn_step]

Well for the low end SRAM (AKA cache) with 180nm process about $95.70 retail..

[Starscream]

wasnt AMD gonna use that new technology wich reduces the size of cache alot (i thought times 5).
so if the cache needs a smaller surface u can get more CPUs per waffer.
wich will reduce the extra cost if u increase the amount of cache?
i mean compaired to current CPUs wich dont make use of the new cache technology.

[nn_step]

wasnt AMD gonna use that new technology wich reduces the size of cache alot (i thought times 5).
so if the cache needs a smaller surface u can get more CPUs per waffer.
wich will reduce the extra cost if u increase the amount of cache?
i mean compaired to current CPUs wich dont make use of the new cache technology.
No it cuts it in half
http://www.us.design-reuse.com/news/news9538.html
and yes small makes it cheaper.. but then again you can't just go to newegg and buy 1MB of L1

[freecableguy]

Does anyone here have any idea how much 1 meg of L1 cache costs to produce?

not as much as you think. I can buy an Opteron 148 for $111 now. The FX57 with the same amount of cache and same silicon is $800+. It's called speed binning/profit maximization. Nothing to do with the cost of tea in China (or the "cost" of 1MB of L2). This was much different years ago but cache nowadays has suprisingly little to do with actual production costs.

-fcg

[Stuperman]

Wouldn't this help AMD with SuperPI, cause it loves bandwidth. But that is assuming the latencies on the L3 cache are not crap (a la intel 5XX-->6XX).

edit: onewingedangel, my CPUZ reports that my L2 cache runs at full speed, did you mean slower in terms of latency?

[nn_step]

Wouldn't this help AMD with SuperPI, cause it loves bandwidth. But that is assuming the latencies on the L3 cache are not crap (a la intel 5XX-->6XX).
Actually Cache's primary job is to mask Ram Latency..

[Thorry]

I do wonder, where do you get these numbers?

Adding an amount of L3 cache at say 1.5 ghz (which would be more then fast enough) including the extra pathways etc would only add max 10 watts of heat energy. When switching to a smaller process they would lose a lot of watts so they can simply add it.

Also with the techniques AMD has bought they can add a lot more cache.

It's just natural, first there was no cache, then external cache, then internal cache, then external level 2 cache, then internal level 2 cache. And now there would be internal level 3 cache. Since the speeds have gone up ways external level 3 cache is not an option (or it's called memory :P) so internal level 3 cache is the key.

[Mikesta]

I seriously think that L3 will be for quad-cores next year. 4 cores sharing dual channel memory (2 cores for each channel) will be a stretch even with high bandwidth DDR2. L3 is a logical choice to help alleviate that.

BTW I 'heard' that the L3 cache will be shared. 4mb shared L3, that's 1mb per core, seems logical (of course some cores will use more and some will use less at anyone time depending on the process).

Now if AMD just shrunk the L2 latency a touch say from 17-14? That is what would be sweet.

[WeStSiDePLaYa]

I seriously think that L3 will be for quad-cores next year. 4 cores sharing dual channel memory (2 cores for each channel) will be a stretch even with high bandwidth DDR2. L3 is a logical choice to help alleviate that.

BTW I 'heard' that the L3 cache will be shared. 4mb shared L3, that's 1mb per core, seems logical (of course some cores will use more and some will use less at anyone time depending on the process).



that seems like the most effecient choice. and to think im using 256kb now!

[Bloody_Sorcerer]

I seriously think that L3 will be for quad-cores next year. 4 cores sharing dual channel memory (2 cores for each channel) will be a stretch even with high bandwidth DDR2. L3 is a logical choice to help alleviate that.

BTW I 'heard' that the L3 cache will be shared. 4mb shared L3, that's 1mb per core, seems logical (of course some cores will use more and some will use less at anyone time depending on the process).

Now if AMD just shrunk the L2 latency a touch say from 17-14? That is what would be sweet.
except socket F (server socket) will most probably be quad channel DDR2.

[AkXb70]

level one is a small extremely fast cache that holds the instructions that are to be fed into the cpu pipeline. l2 is usually half the speed or less of the l1, but is many times larger, and contains both instructions that are to be fed into the pipeline, as well as data that may be required or is being continuously fed in and out of l1. l3 cache serves much the same purpose as l2, and provides more space for data to be held, it is however far slower than l2 again. The main memory feeds the large l3 which feeds the smaller but faster l2, which in turn feeds the smaller and faster l1.

So if you have 8MB l3 you have 8Mb of data stored in a faster than main memory store that the cpu can work with, with the data most likely to be worked on being prioritised and stored in l2, and the instructions to be fed into the cpu stored in l1. Where possible an increase in l2 is preferable to adding l3 as it is much faster and increases the workable data ammount, as the contents of l1 and l2 have to be stored in l3, so you effectively have the size of the lowest level cache, but with faster smaller stores. Increasing l2 gives you more room at a higher speed - this is why a cpu with 2Mb L2 would be preferable to a cpu with 1MB l2 and 2MB l3. However issues with latency when increasing cache sizes beyond certain limits (as well as increasing the likelihood of defects) means that level 2 cache can only be grown so far before you see diminishing returns and this is where l3 cache comes in handy.

Most modern l3 is off die but on chip (a daughter die if you wish), which allows existing cpu designs to have l3 cache added without taping out a new design (eg. mp xeons are a prescott or smithfield core with mp support and added l3) and also increases yields. This is often used in multi-processor xeons to compensate for the lower front side bus speeds, as having a larger local store helps compensate for the slower access to the main store of data held in main memory.
All intel netburst processors with L3 have the L3 incorporated into the die.

ie, galatin cores are not northwoods with a daugter die of L3, they incorporate the L3 on die. same goes with all other MP designs such as potomac and tulsa. take a look at a die scan if you will ;)

this also means they use separate wafers...this isnt like cedar mill where you put 2 chips on a package and it works

[freecableguy]

where you guys get these numbers is beyond me. even extremely high speed GDDR3 (which can be as much as 64MB per chip) only consumes 3-5W. 40W? try again... :slap:

so how much will 4mb of l3 cache consume??

Well, I'd just like to backup what I said before of 3-5W or so. Now, I know that AMD and Intel L3 cache processing is different but in the long-run their separate processes yield very similar results. Here's what I just read from a GREAT article on the new Tulsa CPU from Intel (Xeon MP w/16MB L3 cache):

"Thanks to these optimizations, along with long Le transistors, the L3 cache is extremely efficient; the average power is 12W or 0.75W/MB. "
Taken from this page: http://www.realworldtech.com/page.cfm?ArticleID=RWT021906030756&p=3

So 4MB of L3 cache from AMD will probably be about 4-5W just as I had said. Whoever said that this would add 40W is out to lunch as usual.

-FCG