tight ram timings - very tight indeed - tras=0

[ooztuncer]

Hi all,
I also posted this under dfi-street (http://www.dfi-street.com/forum/showthread.php?t=28196) (nick:ooztuncer).

I can set up my TRAS value to "0" by using big toes 704-2BTA bios. Is it possible, a known issue, or a glitch?

Yesterday I played with my timings (http://www.dfi-street.com/forum/showthread.php?t=28190) and hit some good benchies. However this issue confused my mind.

Hit me!

[s7e9h3n]

LOL...that's not tight ;) This is tight:
http://img437.imageshack.us/img437/6585/11x2741m0nc.jpg

[Vapor]

What? Not trtw at 1? Pfff.

Those are excellent timings Steve....ESPECIALLY at that speed :up:

[s7e9h3n]

What? Not trtw at 1? Pfff.

Those are excellent timings Steve....ESPECIALLY at that speed :up:
LOL....trtw1 won't work past 250 ;)

[ooztuncer]

i agree they are really good, but what I am interested is can tRAS set to "0" (apparently yes). I am just confused because I always thought memory bank's minimum row active time should be > 0.

[freecableguy]

Set your Read Preamble to 4.0ns and disabled your Dynamic Idle Cycle Counter. You can also set your CAS latency to 1.5 clocks (1.0*) for a bling factor. :D

EDIT: BTW, Tras at 0 is the best match for a low Idle Cycle Counter (like 0-8)...

EDIT 2: stephen...YOUR timings look good, I look at the wrong post...in that case my information above is for you! ;)

[s7e9h3n]

Set your Read Preamble to 4.0ns and disabled your Dynamic Idle Cycle Counter. You can also set your CAS latency to 1.5 clocks (1.0*) for a bling factor. :D

EDIT: BTW, Tras at 0 is the best match for a low Idle Cycle Counter (like 0-8)...

EDIT 2: stephen...YOUR timings look good, I look at the wrong post...in that case my information above is for you! ;)
Haven't yet tried RP @ 4, but afaik, if you disable DICC, you may be able to sqeeze a couple of more mhz, but you definately will be slower clock for clock.....

[Eldonko]

You can set tras 0 with pretty much any bios, its no glitch. It is like cas 1.5 though, not supported. I found tras = 0 gave me added stability at the top end of RAM speed, but it does nothing for performance.

[Vapor]

I found the opposite with tras 0....it helps quite noticably in SPI and I lost some stability.

[STEvil]

depends heavily on the cpu/mobo/bios/memory as to how it will react to 0 tRAS.

TRCD and TRP are where some big gains are hiding.

[Eldonko]

I found the opposite with tras 0....it helps quite noticably in SPI and I lost some stability.Got curious when I read your post and tested 5 runs at tras 6, 5 at tras 0. Difference is within margin of error.

http://members.shaw.ca/zryan/test-3.JPG

[Kasparz]

http://fotki.lv/fotki/all/4/371/37087/151022/1302945287450.jpg
Look ar A64Tweaker screen :D
But i can't pass 270Mhz :p:

[s7e9h3n]

Set your Read Preamble to 4.0ns and disabled your Dynamic Idle Cycle Counter. You can also set your CAS latency to 1.5 clocks (1.0*) for a bling factor. :D

EDIT: BTW, Tras at 0 is the best match for a low Idle Cycle Counter (like 0-8)...

EDIT 2: stephen...YOUR timings look good, I look at the wrong post...in that case my information above is for you! ;)
OK, I tried rp@4 and it actually gave me slower times than @ 4.5. Kinda weird, but I tested a few times and it consistently gave worse results :confused:

[1031.nu]

http://fotki.lv/fotki/all/4/371/37087/151022/1302945287450.jpg
Look ar A64Tweaker screen :D
But i can't pass 270Mhz :p:

All this talk about memory made me try out timings .. your runing a faster chip than I am but check this out.

http://1081gaming.com/pics/33516pi.jpg

[Vapor]

Got curious when I read your post and tested 5 runs at tras 6, 5 at tras 0. Difference is within margin of error.

http://members.shaw.ca/zryan/test-3.JPGHmm....I've never actually tested tras 6 vs 0....only 5 and 0, could 6 be faster than 5 in SPI? I also typically get .01-.05 difference, what are your other timings? My observations were with TCCD @ 2.5-3-3, btw, not BH/CH like I'm assuming yours were at.

[1031.nu]

Hmm....I've never actually tested tras 6 vs 0....only 5 and 0, could 6 be faster than 5 in SPI? I also typically get .01-.05 difference, what are your other timings? My observations were with TCCD @ 2.5-3-3, btw, not BH/CH like I'm assuming yours were at.

My scores went down with a TRAS at 0. I find 3 to net the best score for me.

[mad mikee]

What happens when you set it to 0 is that is like a 'use default settings (SPD?) Flag, seems to work here, not sure about other parameters. Sorta like what ElDonko was saying :hehe:
Hope this helps mad :nuts: mikee


Hi all,
I also posted this under dfi-street (http://www.dfi-street.com/forum/showthread.php?t=28196) (nick:ooztuncer).

I can set up my TRAS value to "0" by using big toes 704-2BTA bios. Is it possible, a known issue, or a glitch?

Yesterday I played with my timings (http://www.dfi-street.com/forum/showthread.php?t=28190) and hit some good benchies. However this issue confused my mind.

Hit me!

[ooztuncer]

You can set tras 0 with pretty much any bios, its no glitch. It is like cas 1.5 though, not supported. I found tras = 0 gave me added stability at the top end of RAM speed, but it does nothing for performance.

Thanks for the information guys. As many of you mentioned between tras 0 and 8 I did notice really small gains/losses. Set it to 5 in the end. Here is the latest update (ram at 243 using 3.1 volts):

http://i9.photobucket.com/albums/a87/ooztuncer/finalram.jpg

[Kasparz]

My scores went down with a TRAS at 0. I find 3 to net the best score for me.
What mem you have?
I couldn't run my CH5@270@spi1m stable
More than 3.5Vdimm doesn't help.