dual channel memory and amd

[bwanaaa]

my question is whether the first dual channel pair are handled preferentially by the on-die mem controller than the second dual channel pair? Is there a preference or speed advantage to one pair?

This begs the question of why the timings are slower when all 4 slots are populated. any insight on this?

[largon]

Afaik command rate is the only timing that is automatically lowered to 2T if 4 slots are populated with double sided dimms.

[eddieate]

its true ^^
/Ed

[bwanaaa]

so i guess the 2 dual channel pairs are equal. i was wondering if the second pair served as overflow to the first only?

[saratoga]

so i guess the 2 dual channel pairs are equal. i was wondering if the second pair served as overflow to the first only?

I believe they're electrically wired in parallel. So having 1 DIMM in a channel is just like having 2 at half the size. The downside is the extra DIMM slows down signals passing through the bus a little, which is why the timings are slightly worse if you have 2 double sided DIMMs.