Dfi-nf4 + Ocz Vx

[[VII]]

Hey guys...

today my OCZ VX PC4000 just arrived...before i used OCZ TCCDs...

my first test was 2-2-2-8@1T @ FSB250 @ 3,45V

But i've got errors in memtest ...

Has anyone good DFI-SLI-DR Settings for OCZ VX?

THX 4 help

sry 4 my bad english...i am from germany

[VII]

[loc.o]

Have a look at Tref. Mine like Tref 1168 on volts above 3,3v. These are me settings with bios 510-2fix.

Genie BIOS Settings:
FSB Bus Frequency - 250
LDT/FSB Frequency Ration - 3
CPU/FSB Frequency Ratio - 12
PCI eXpress Frequency - 100Mhz

DRAM Voltage Control - 3.50v

DRAM Configuration Settings:
DRAM Frequency Set - 200 (DRAM/FSB:1/01)
Command Per Clock (CPC) - Enable
CAS Latency Control (Tcl) - 2.0
RAS# to CAS# delay (Trcd) - 02 Bus Clocks
Min RAS# active time (Tras) - 05 Bus Clocks
Row precharge time (Trp) - 02 Bus Clocks
Row Cycle time (Trc) - 07 Bus Clocks
Row refresh cyc time (Trfc) - 16 Bus Clocks
Row to Row delay (Trrd) - 02 Bus Clocks
Write recovery time (Twr) - 02 Bus Clocks
Write to Read delay (Twtr) - 01 Bus Clocks
Read to Write delay (Trwt) - 02 Bus Clocks
Refresh Period (Tref) - 1168 Cycles
Write CAS Latency (Twcl) - Auto
DRAM Bank Interleave - Enabled

DQS Skew Control - Auto
DQS Skew Value - 0
DRAM Drive Strength - Level 8
DRAM Data Drive Strength - Level 4
Max Async Latency - Auto
Read Preamble Time - Auto
IdleCycle Limit - 16 Cycles
Dynamic Counter - Disable
R/W Queue Bypass - 16 x
Bypass Max - 07 x
32 Byte Granularity - Disable(8 Bursts)

[HiJon89]

I just opened my set of VX4000 and popped into my Ultra-D. I cranked it up to 250Mhz 3.2V and got 0 errors after 9 hours of Memtest test #5 using these settings (I'm using a 3700+ San Diego BTW, not an FX-55) These timings are about as tight as you can get, they should give just about the most bandwidth possible:

Genie BIOS Settings:
FSB Bus Frequency - 250
LDT/FSB Frequency Ration - 4
CPU/FSB Frequency Ratio - 11
PCI eXpress Frequency - 100Mhz

DRAM Voltage Control - 3.20v

DRAM Configuration Settings:
DRAM Frequency Set - 200 (DRAM/FSB:1/01)
Command Per Clock (CPC) - Enable
CAS Latency Control (Tcl) - 2.0
RAS# to CAS# delay (Trcd) - 02 Bus Clocks
Min RAS# active time (Tras) - 05 Bus Clocks
Row precharge time (Trp) - 02 Bus Clocks
Row Cycle time (Trc) - 07 Bus Clocks
Row refresh cyc time (Trfc) - 14 Bus Clocks
Row to Row delay (Trrd) - 02 Bus Clocks
Write recovery time (Twr) - 02 Bus Clocks
Write to Read delay (Twtr) - 01 Bus Clocks
Read to Write delay (Trwt) - 02 Bus Clocks
Refresh Period (Tref) - 2592 Cycles
Write CAS Latency (Twcl) - 1
DRAM Bank Interleave - Enabled

DQS Skew Control - Auto
DQS Skew Value - 0
DRAM Drive Strength - Level 5
DRAM Data Drive Strength - Level 2
Max Async Latency - 6ns
Read Preamble Time - 4.5ns
IdleCycle Limit - 16 Cycles
Dynamic Counter - Enable
R/W Queue Bypass - 16 x
Bypass Max - 07 x
32 Byte Granularity - Disable(8 Bursts)

[[VII]]

ok...i've just play a little with the settings...and now i've got the following result...

http://www.mweis.org/image/SuperPi_1M_fsb250.jpg

http://www.mweis.org/image/SuperPi_32M_fsb250.jpg

is that ok?

[VII]

[Big Deel]

Lower the volts and retest,some vx dosn't like over 3.3 @ 250.