Mem timings: nanoseconds or clock pulses?

[Gogar]

Some people seem to think that 2 2 2 5 @ 200MHz has lower latency than say 2.5 3 3 8 @ 300MHz. But i have my doubts about that.

If the timing numbers are clock pulses then
2 2 2 5 in nanoseconds is 10 10 10 25 ns

2.5 3 3 8 @ 300MHz would be 8.33 10 10 26,66 ns

Pretty much the same.. except the CAS latency is even lower.

Is this correct?

[targ]

clock cycles, as far as im aware it is any way.

and it would be to the local clock freq, so based on the ram freq not the cpu etc.

targ

[Gogar]

Maybe someone would like to test memory latency for me running
2 2 2 6 @ 12x200=2400MHz and 3 3 3 9 @ 8 x300=2400MHz. My own ram can't do those speeds. :)

[RyderOCZ]

Your 300 MHz example would win, I think.....at least in an everest measurement.

I will see what I can do about comparison :)

[Gogar]

Awesome :up: Aren't you OCZ guys supposed to be real busy though? ;)
Thanks for any input. :) It's just interesting..

Some review once compared performance of memory with tight timings at a low fsb, and then loose timings at a high fsb. And then they concluded that high latency with more bandwidth is better. But to me it seems they didn't increase the latency at all because the clock pulses got shorter, they just increased bandwidth.

I'm just trying to get an understanding of it all, and maybe i'll make a calculator that can suggest optimal settings for specific applications.

I bet bandwidth wise 300fsb will win, i'm just not sure about latency, especially if the cpu frequency is the same. Any decrease in latency going from 200 to 300 with the same timings in nanoseconds would be caused by the higher frequency of the memory controller.

Say @ 200 you get 45ns total memory latency and @ 300 you get 40ns

That means going from 200 to 300 which is like cutting one sixth off the clock pulse length 1/2 - 1/3 = 3/6 - 2/6 = 1/6
this gives you a 5ns decrease...
So then you could estimate the total latency of the memory controller alone:
3x3 = 9ns (200MHz) and 2x3 = 6ns (300MHz)
These are just fictional values though. (It's 8am here though and i haven't gone to bed yet so don't shoot me for any errors please ;) )

I think i also understand now why people think increasing the frequency increases performance so much more than just increasing the CAS latency.
The CAS latency is only a small part of the total latency of a memory access.
Increasing the frequency decreases the latency of ALL timings together, so it obviously has a much greater effect.

[Jimbo Mahoney]

This is a very good point Gogar.

I'd forgotten that the timings are clock cycles, therefore higher clock speed compensates in terms of latency too.

I tried to do your test, but I cannot get my memory to run @ 300 Mhz 3-3-3-9. I have to drop to something like 3-4-4-10, but that goes as high as 325 Mhz

[Cornelious0_0]

I tried to do your test, but I cannot get my memory to run @ 300 Mhz 3-3-3-9. I have to drop to something like 3-4-4-10, but that goes as high as 325 Mhz

Too bad...I might do some checking in on this.....I can do 2.5-3-3-5 @ 2.7v with my 4400LE 431 2x256MB, and 2-2-2-5 at PC3200 easily.

[Jimbo Mahoney]

Interesting article from Corsair here:

http://www.corsairmemory.com/corsair/products/guides/AN501_Latency_Settings_and_Performance.pdf

It shows the effects each timing has.

Summary:

2-2-2-5 1T as reference point:

increasing CAS + 1 = 2.5% hit

increasing tRCD + 1 = 2.25% hit

increasing tRP + 1 = 0.66% hit

increasing tRAS + 1 = 0% hit

increasing CPC + 1 = 3.3% hit

Using Gogar's hint that timings are (of course) based on the clockspeed and these weightings, I can work out the likely equivalent latency of high speed (slack timings) RAM vs low speed RAM (tight timings).

e.g.

225 Mhz @ 2-2-2-6 1T = total latency of 35.5 ns (theoretical, based on total latency = CAS + tRCD + tRP + 2 clock cycles and 225 Mhz = 4.44ns per cycle)

324 Mhz @ 3-4-4-10 1T = 40.1ns

= 14% increase

BUT

If you weight them according to that article:

225 @ 2-2-2-6 1T = 48.4 (arbitrary number now)

324 @ 3-4-4-10 1T = 59

= 22% increase

Hope someone understands my logic...

[EMC2]

Jimbo...

Don't forget that there is a difference between latency and performance metrics ;) You can have low latency and still have much less than optimal performance as exhibited by running programs (for example - the effect of interleaving or the effect of refresh rates and cycle times).

Remember when looking at performance, it isn't as simple as adding up the basic timing clock counts... you have to look at the big picture and the various types of complete memory cycles that are in play.

Peace :toast:

[Dumo]

Heres the comparo....not optimize
tccd @335 and +100mhz on cpu with 3.1V >< bh-5@271 with 3.6V....
http://img286.echo.cx/img286/4949/superpi9ks.jpg
http://img286.echo.cx/img286/7011/superpi28tn.jpg

[Cornelious0_0]

Go TCCD!!! :banana:

[uscfan]

This is so confusing. All I know is, 2-3-2-6 and 2-2-2-5 are not too far apart, if we go by nanoseconds. Think about it, a nano second!!! So really are we going to notice performance increases other than in sandra? If I ever have a child I will defenitly not name her Sandra.

[Jimbo Mahoney]

Jimbo...

Don't forget that there is a difference between latency and performance metrics ;)

I know dude.

I'm not saying that low timings are everything, just weighting the effect of each particular timing.

I always try to maintain correct timings and achieve the highest memory speed for those timings.

ie some people seem to think that just setting the lowest settings willynilly will be the best.

Think about it, a nano second!!! So really are we going to notice performance increases other than in sandra?


Are you saying that because the difference in timings is measured in nanoseconds that we won't notice this because a nanosecond is such a short time period?

If so, that is not correct. Apologies if that isn't what you are saying.

However, you are pretty much correct that memory timings won't really be noticeable in games for example. The difference between the best and worst timings (at the same clock speed) is perhaps 5%. Whether you'll notice this 5% in games is questionable, but it has nothing to do with the fact memory times are measured in nanoseconds.

[hipro5]

Heres the comparo....not optimize
tccd @335 and +100mhz on cpu with 3.1V >< bh-5@271 with 3.6V....
http://img286.echo.cx/img286/4949/superpi9ks.jpg
http://img286.echo.cx/img286/7011/superpi28tn.jpg

Just consider that if you run your CPU with the BH ALSO at 3350MHz, you would be something like 24.xxx seconds...........So BH at 271MHz will overtake the TCCDs at 335MHz.......... ;)

[Gogar]

I guess what i'm wondering is, whether the performance increase you get from increasing the memory clock comes from the increased bandwidth or the reduced latency.

I want to find out how big the performance increase is from latency or bandwidth separately.

And also can you really say that if bandwidth increases a% then performance increases b%?
Isn't it just that an application requires a certain amount of memory bandwidth and doesn't use any more?
Kind of like downloading, if the server you download from only gives you 100KB/s then it doesn't matter if your DSL can do 4Mbit or 8Mbit.

Then again if a program needs to store 100MB in the memory, with more bandwidth this will complete faster so the transaction as a whole would have lower latency.

I've decided it's a bit too complicated to try to pick apart ;)

Hopefully i can just train a neural network how to get the best performance by learning from benchmark feedback by users.

I just need to know whether ram will work when you do:
- get your tightest timings in nanoseconds for CAS TRCP and TRP
- get the max ram frequency with the loosest timings
- pick a random memory frequency below your max
- figure out the timings that should work at that frequency by looking at the nanosecond timings.

I tried to do your test, but I cannot get my memory to run @ 300 Mhz 3-3-3-9. I assume 2 2 2 6 did work. So i guess that means what i was talking about doesn't work. Maybe there are other timings that if left unchanged cause instability at a higher frequency?

[Cornelious0_0]

I assume 2 2 2 6 did work. So i guess that means what i was talking about doesn't work. Maybe there are other timings that if left unchanged cause instability at a higher frequency?

Most likely...I saw quite a bit of that when I was playing with my memory on this Ultra-D. With my Venice, two things that gained me a fair bit of stability at higher ram clocks was setting the DQS down to 128, and disabling Bank Interleaving.