Lynnfield P55 - B2B Performance

[FUGGER]

A brief explanation into Back to Back Cas Delay settings and gaining more performance or showing of high memory speeds without bandwidth.

Intel i7 870 @ 4Ghz 30c
200x20 @ 1.3v
QPI/Vtt 1.1v
HT ON
EIST OFF
C1E OFF
TURBO OFF

Kingston 1600C9 @ 2000C9
Elpida 1.74v

Gigabyte p55 UD6
F4E bios

B2B setting of 1 (http://fugger.netfirms.com/b2b/b2b1.JPG), set in bios, shows as #disabled in CPU-Tweaker

B2B setting of 6 (http://fugger.netfirms.com/b2b/b2b6.JPG), set in CPU-Tweaker

B2B setting of 12 (http://fugger.netfirms.com/b2b/b2b12.JPG), set in CPU-Tweaker

B2B setting of 32 (http://fugger.netfirms.com/b2b/b2b32.JPG), set in CPU-Tweaker

The major problem is when you use the upper memory rations the B2B setting will be dropped back to 12 in most cases if left on auto.

The Intel p55 board does now allow manual setting of the B2B in advanced memory timing.

Elipda, Samsung, and Micron all could function at speed with B2B bios setting of 1 or 4 in CPU-Tweaker

Tightened 32M (http://fugger.netfirms.com/32m4.JPG)

[TheGoat Eater]

hmm - didn't realize you could use such a tight B@B setting as 1 - must try now LOL

Thanks for the info!

[dinos22]

i love the bandwidth in B2B=32 :ROTF:

[hicookie]

i love the bandwidth in B2B=32 :ROTF:


B2B:31 for super high memory clk using elpdia BBSE:)

[RPGWiZaRD]

B2B cas delay is like the new Performance Level setting except it only radically affects bandwidth only. It's good that Gigabyte works fine with CPU Tweaker and doesn't require any special bios and allows changing B2B in bios (for a value less than 4 as well). :) You can get nice performance already at DDR3-1600 CL6-7 with B2B: 1.

BTW if you don't mind if I'm asking (don't feel like sending a PM) what's the vdroop of the gigabyte board like, I know you mentioned MSI GD80 got like 0.01v.

[massman]

For those who need more than the brief explanation, I wrote about this timing 2 months ago: http://www.madshrimps.be/?action=getarticle&articID=940

B2B is what you want to adjust when the 6x memory multiplier is bugged ... hehe

[Raja@ASUS]

B2B sets a delay for the number of memory clock cycles to pass before a read is processed.

Values below 4 don't work on i7 (apart from 0 to disable the logic), so 1-3 will default to 4.

RTL is the number of Uncore clocks that pass before data arrives at a pad in the IMC.

Main performance is locked away in the post equation (some of these parameters are available to adjust).

[Leeghoofd]

Are the Asus boards still locked for manual input via the Felix Tweaker tool ?

[hiwa]

B2B sets a delay for the number of memory clock cycles to pass before a read is processed.

Values below 4 don't work on i7 (apart from 0 to disable the logic), so 1-3 will default to 4.

RTL is the number of Uncore clocks that pass before data arrives at a pad in the IMC.

Main performance is locked away in the post equation (some of these parameters are available to adjust).

:clap::clap::clap: thanks for info Raja

Good tests charles high B2b for higher mem freq

[Chri$ch]

Are the Asus boards still locked for manual input via the Felix Tweaker tool ?
works well with Asus P7P55D Deluxe

http://img1.abload.de/img/b2b-3o3r0.jpg

http://img1.abload.de/img/b2b-193il.jpg

[Leeghoofd]

Thanks Crisch :) Wished they did the same with the X58 ones (though haven't tested the latest biosses there)

[TheGoat Eater]

where did you get CPU Tweaker 1.3.1 beta ? as I can't find it

[Leeghoofd]

CPU-Tweaker13b1.zip (http://www.tweakers.fr/download/CPU-Tweaker13b1.zip) Is that the one ? Can't open the file on a S478 rig here:p

[Sertain]

[QUOTE=FUGGER;4001803]A brief explanation into Back to Back Cas Delay settings and gaining more performance or showing of high memory speeds without bandwidth.

Hey Fugger,
Toss in a screen shot of the bios page that you tweaked please.

And have you tried this on the X58 Gigabyte board?

-Sertain

[FUGGER]

I can do and yes I have tried and it works (needs to be locked down) on GBT.

[Brama]

Thanks Crisch :) Wished they did the same with the X58 ones (though haven't tested the latest biosses there)

R2E with latest BIOS 1504 is still locked. :(

[FUGGER]

I have an update from Intel, requested permission to post.

One of the XMP engineers goes into B2B, JEDEC and tCCD.

B2B with a setting of 3 tCLK??

R2E can adjust B2B, just started playing with it.

"When I first wrote the XMP spec, I added 4 new parameters to kind of expose these turn around times to overclockers. They were Read to Read, Read to Write, Write to Read and Write to Write pull-in / push-out parameters. So far, I haven’t seen any Module suppliers take advantage of these parameters but..."

[Raja@ASUS]

In all seriousness, there is no real need to adjust this spacing to anyone's real advantage - you just waste clock cycles on concurrent reads. If the vendors did take 'advantage' of this setting you'd see higher speed kits which in reality run at lower levels of performance - is this what people need? The bigger deal here as it has always been is the tRD, which is not B2B btw.

Default B2B spacing is the width of the bus (4 clocks for i7 and i5, the GB setting of 1 is default; 4 clocks, they just shifted the table to make more sense to overclockers) - as fast as you can go. For all benches that actually score something, this is where you need it to be. The same goes for any other physical rank to rank delays.

[Leeghoofd]

Does Felix's tool got acces now from the Asus engineers ? or are you adjusting via the bios itself ? (B2B setting was in there from release bios)

[FUGGER]

Raju, True but I provided proof that some high end dram needed the top memory ratio (at low or stock bclk) and the auto bios setting the B2B value to 12 or higher and the answer I got was "it is not supposed to do that" yet this can be seen on three of the boards I tested.

"I didn’t’ add it to XMP and haven’t suggested that OEM/ODM’s add it as a bios parameter.
If someone changes that value in the bios, what it REALLY is doing is affecting the tRead time, or total turn around time for a read parameter. The tREAD time is a composition of multiple DRAM and system timing parameters and modifying any one of them past it’s normal parameter “could” artificially reduce the tREAD time. I say COULD because some BIOS vendors and certain chipsets can put a limit on how large a specific parameter range is AND some memory controllers don’t even give a parameter for tCCD and just hard code it to 4 (which is the case in SEVERAL platforms)."

Its something that we did not see on previous platforms as an issue and even some of the guys here made this mistake and you didnt catch it even though you responded and acknowledged the results as correct, boble's thread where he ran 2300Mhz cas 8 and it was faster than 2300Mhz cas 7 by a large margin... I didnt want to make an example of anyone let alone other sites (gave some sites time to fix/add). Later in that tread (after this thread) you were all over B2B.

We had Hicookie showing off absurd memory clocks by exploiting this, I never explored the higher value with bclk but I wouldnt be surprised if this allows higher blck with 12+ setting.

I also gave live demo on this with Kingston, Intel and Gigabyte on reaching highest memory speeds as well as why the Kingston demo had poor bandwidth where I could beat it with low end memory at stock speed.

[Raja@ASUS]

Its something that we did not see on previous platforms as an issue and even some of the guys here made this mistake and you didnt catch it even though you responded and acknowledged the results as correct, boble's thread where he ran 2300Mhz cas 8 and it was faster than 2300Mhz cas 7 by a large margin... I didnt want to make an example of anyone let alone other sites (gave some sites time to fix/add). Later in that tread (after this thread) you were all over B2B.





I think you are refering to the Corsair/Gskill threads, where CAS 6-7 @ 2K+ got ousted by CAS 8-8 @ 2.4K+ and not cas 8-9 in 32m. This has nothing to do with B2B cos it is disabled at both performance points. Only thing I've always explained is that this is not by definition tRD, yes it will affect the readback time on B2B reads by definition, but not the initial memory access time. Even back there before your thread btw;

http://www.xtremesystems.org/forums/showpost.php?p=3892281&postcount=13

ns in that post should be replaced with clocks though.

What I will acknowledge is that some boards set it up looser than it needs to be (you were right to point that out - I think Massman should have the credit for that though), other than that it's not something that really stoked my fire in terms of performance.

[FUGGER]

2300Mhz cas 7 (http://boblemagnifique36.free.fr/Hardware/Memory/Corsair2200c8/Corsair2200c8/Corsair2200C8/1155c7.jpg)

2300Mhz cas 8 (http://boblemagnifique36.free.fr/Hardware/Memory/Corsair2200c8/Corsair2200c8/Corsair2200C8/1170c8.jpg)

no BW screen, cpu-tweaker, or mention of settings but I have a strong suspicion that the B2B setting was on auto and it running a higher value than 4.

[Raja@ASUS]

I have the board here and have not seens an insatnce in which B2B shifts as of yet, unless he chanced on something. My comments in that thread had nothing to do with those particular results btw - they were about my CAS 6 2k+ vs Benni'es straight 8's at 2.4K.

[FUGGER]

Link it, Im not sure what you are referring to.

When I get get back on P55 I will force it and post my method and bios version.

[Raja@ASUS]

http://www.xtremesystems.org/forums/showpost.php?p=3998089&postcount=25

that talking about vs me running Cas 6-7 over 2K

I checked all the B2B stuff on my board - it was disabeld at all times. To cut to the chase, CAs 6-7-6 over 2000 beat CAS 8-9-8 over 2400MHz, but CAS 6 did not beat CAS 8-8 over 2400. B2B was disabled all the time on the EVGA 657.

[massman]

What I will acknowledge is that some boards set it up looser than it needs to be (you were right to point that out - I think Massman should have the credit for that though), other than that it's not something that really stoked my fire in terms of performance.

;)

The reason why I mentioned tRD in the initial article was mainly because the B2B seemed to have pretty much the same behavior (when put to practive) as tRD had on C2D. That and the fact that it refers to something related to 'read delay' ... well, it's just easy to use the analogy.

The most interesting part about B2B is, in my humble opinion, that it makes high-end memory kits absolutely obsolete for anything but extreme overclocking.

Btw, has anyone checked the bandwidth troughput of Elpida Hyper and Micron? Running the exact same freqs/timings, my Micron kit consistenly hits higher bandwidth figures.

[Raja@ASUS]

;)

The reason why I mentioned tRD in the initial article was mainly because the B2B seemed to have pretty much the same behavior (when put to practive) as tRD had on C2D. That and the fact that it refers to something related to 'read delay' ... well, it's just easy to use the analogy.

The most interesting part about B2B is, in my humble opinion, that it makes high-end memory kits absolutely obsolete for anything but extreme overclocking.



Btw, has anyone checked the bandwidth troughput of Elpida Hyper and Micron? Running the exact same freqs/timings, my Micron kit consistenly hits higher bandwidth figures.

The spacing can normally be left to 4 clocks without any issues so long as the boards are setup properly. In such instances, the lower tCL and increased bw does not make running 2000+ speeds' completely stable' obsolete at all on capable kits. The majority of system performance comes from random access of memory. ALthough I'm sure some vendors would be thankful to hear it. The fact you can completely disable the additive logic pretty much tells you how much importance this function really has.

[massman]

I'm talking about anything that doesn't involve pushing for the extra 200 points or trying to shave off another 6 seconds of your PI.

[Raja@ASUS]

The context of high end kit usage is generally geared towards extreme use, within that context, the high end stuff (especially the lighter capacitive load modules) come out on top for more than one reason.

[NoDsl]

So, b2b is like performance level but instead of loosening the chipset is loosening the memory respectivly with performance loss?

[Raja@ASUS]

It adds extra DRAM clock cycle delays on back to back reads. Primary tRD is setup according to the initial CAS/RAS access time (and other variables, ie the time it takes to issue the command acording to the chipset topology). Given the choice, you'd want to lock the B2B delay to the minmum spacing, and concetrate on reducing the inital access time if possible. Of course, one could argue memory performance has little impact on everyday system performance, but that does not stop people from overclocking.

[massman]

The spacing can normally be left to 4 clocks without any issues so long as the boards are setup properly. In such instances, the lower tCL and increased bw does not make running 2000+ speeds' completely stable' obsolete at all on capable kits. The majority of system performance comes from random access of memory. ALthough I'm sure some vendors would be thankful to hear it. The fact you can completely disable the additive logic pretty much tells you how much importance this function really has.

Hm, I reckon there's a difference between 1156 and 1366 platforms when it comes to this. Let me rephrase then:

For anything but extreme overclocking, or in a wider spectrum absolute highest performance, I couldn't recommend high-end memory kits to anyone. On 1366, you'll notice very little difference between a 1333 kit or 2000 kit using the same memory frequencies in applications that are not especially coded to measure memory bandwidth. I should check to be entirely sure, but the difference between 1333 and 2000 was about 5% overall (as published in the last memory round-up at Madshrimps - I am not the author).

On 1156 things may shift a bit, although I don't have any specific data on this. What bothers me a lot is that the massive memory bandwidth is limited by the locked uncore multiplier in the first place.

I could be misunderstanding your message but I hope you're not saying that there's, besides extreme use as you call it, a valid reason why people should be investing in high-end memory kits?

[Raja@ASUS]

Hm, I reckon there's a difference between 1156 and 1366 platforms when it comes to this. Let me rephrase then:

For anything but extreme overclocking, or in a wider spectrum absolute highest performance, I couldn't recommend high-end memory kits to anyone. On 1366, you'll notice very little difference between a 1333 kit or 2000 kit using the same memory frequencies in applications that are not especially coded to measure memory bandwidth. I should check to be entirely sure, but the difference between 1333 and 2000 was about 5% overall (as published in the last memory round-up at Madshrimps - I am not the author).

On 1156 things may shift a bit, although I don't have any specific data on this. What bothers me a lot is that the massive memory bandwidth is limited by the locked uncore multiplier in the first place.

I could be misunderstanding your message but I hope you're not saying that there's, besides extreme use as you call it, a valid reason why people should be investing in high-end memory kits?

There is hardly any diff over 1333MHz on either platform for 24/7 use.

If you're refering to hig end memory and 24/7 systems, I think it's been like that for a long long time. The law of diminishing returns kicks in very quickly. The high end kits are always best left for the hard push overclocking, or in cases where you need additional core speed by reducing load on the IMC (using less capacitive IC's), in which case they are not obsolete just becasue a certain board is screwing around with B2B when it does not have to.

[massman]

Maybe I should change the word "obsolete" to "less interesting" then :p: