Another Leaked AMD Desktop CPU Roadmap

[JumpingJack]

This one from VR-Zone... appears to be the same as what has floated around before, but a few more slides of details....

http://www.vr-zone.com/articles/AMD_Desktop_CPU_Roadmap/6046.html

http://resources.vr-zone.com//newspics/Sep08/12/amdcpuroadmap2.png

[BulldogPO]

What's that Probus?

[LightSpeed]

Deneb without the L3 cache

i hope they release the parts on time this time around. i really do

[duploxxx]

this is the correct roadmap :)

funny nobody mentioned/noticed the change in dualcore... its no longer a k10 but its actually an improved brisbane k8 on 45nm with new mem controller and 1mb cache/core

small die, low cost.

[JumpingJack]

this is the correct roadmap :)

funny nobody mentioned/noticed the change in dualcore... its no longer a k10 but its actually an improved brisbane k8 on 45nm with new mem controller and 1mb cache/core

small die, low cost.

Interesting, nice dig on the detail.

Are you suggesting that Kuma is not the dual core launch?

[The Coolest]

this is the correct roadmap :)

funny nobody mentioned/noticed the change in dualcore... its no longer a k10 but its actually an improved brisbane k8 on 45nm with new mem controller and 1mb cache/core

small die, low cost.
Indeed, quite interesting.
This chip seems to be a shrink of the CPU in their Puma platform, K8 cores with K10\K10.5 NB.

[informal]

this is the correct roadmap :)

funny nobody mentioned/noticed the change in dualcore... its no longer a k10 but its actually an improved brisbane k8 on 45nm with new mem controller and 1mb cache/core

small die, low cost.

I don't think that Regor is a Brisbane derivative.My guess is that its a native dual core K10.5,without L3,making it fast and cheap at the same time.

[Macadamia]

No, the Regor design is VERY CLOSE to Deneb.

The reason why L3 is ditched is because AMD is using the exact same cells for L2 and L3. Why cripple yourself when you don't need the hierarchy in a dualcore?

[duploxxx]

Interesting, nice dig on the detail.

Are you suggesting that Kuma is not the dual core launch?

kuma are disabled agena and toliman's, so yes they exist :)

No, the Regor design is VERY CLOSE to Deneb.

The reason why L3 is ditched is because AMD is using the exact same cells for L2 and L3. Why cripple yourself when you don't need the hierarchy in a dualcore?

so you are stating that they can change the l3 cache to l2 cache just like that? it has 1mb cache/core.... that's double l2 cache from k10 and k10.5

[Macadamia]

No, it has to be a new design. But it's easy to do.

But in a dual core native design where you don't need a victim cache to share with 3 other CPUs, it works. In fact, it might even give a boost compared to current dual core Phenoms.

[Macadamia]

Yay, retarded Photochops with mostly accurate ruler measurements.

The +/- percentage is because I cut some HTT bridge stuff, but the core could be more compact after all.

http://img131.imageshack.us/img131/4962/regorguessli4.jpg

[gOJDO]

No, the Regor design is VERY CLOSE to Deneb.Are you just guessing?

The reason why L3 is ditched is because AMD is using the exact same cells for L2 and L3.The cells are the same, but not the logic working behind them. The L2 & L3 logic on the K10 are so much different.

Why cripple yourself when you don't need the hierarchy in a dualcore?The L3 is not needed for communication between the cores on K10(be it dual, tripple or quad core).

No, it has to be a new design. But it's easy to do.

But in a dual core native design where you don't need a victim cache to share with 3 other CPUs, it works. In fact, it might even give a boost compared to current dual core Phenoms.

The K10 quadcore CPUs don't need the L3 to communicate. They could do that same as K8 is doing, via the RAM. The shared L3 can only boost performance(on single, dual, tripple and quad core CPU) since it is faster than the RAM.

[Macadamia]

They need the L3 to share data. Obviously though, accessing shared data through RAM is nothing near the L3 performance.

The logic is different- it can't possibly be the same, but I was implying that you do little help to use L3 in a dualcore design that does not save space when L2 brings little penalties overall in a DC (not even power usage or heat is that big of an issue relatively speaking)

What would the design be, pray tell, if it's not a derivative of K10(.5)? A cache enhanced Brisbane? :)

[The Coolest]

They need the L3 to share data. Obviously though, accessing shared data through RAM is nothing near the L3 performance.

The logic is different- it can't possibly be the same, but I was implying that you do little help to use L3 in a dualcore design that does not save space when L2 brings little penalties overall in a DC (not even power usage or heat is that big of an issue relatively speaking)

What would the design be, pray tell, if it's not a derivative of K10(.5)? A cache enhanced Brisbane? :)

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Indeed, quite interesting.
This chip seems to be a shrink of the CPU in their Puma platform, K8 cores with K10\K10.5 NB.

"seems to be" probably needs to be replaced by "may be", but it's possible.

BTW K8 cores communicate via the Crossbar.

[Macadamia]

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V



"seems to be" probably needs to be replaced by "may be", but it's possible.

BTW K8 cores communicate via the Crossbar.

That would make perfect sense for mobile (issues not ironed yet?), but the Deerhound core gives AMD a legitimate performance increase without much more die overhead, there is little reason to use the existing Brisbane design.

I do not think that the extra 15-25% IPC increase that the K10 brought was solely/mostly dependent on the L3.

[Sumanji]

Seems there is a TDP drop going from AM2+ to AM3? Either that or they are releasing slower models of Deneb on AM3 initially in February, then moving onto the faster AM2+ speeds in March?

[gOJDO]

They need the L3 to share data. The L3 data on the K10 can be shared or not-shared. It is used for core-to-core communication, but that is not the only way the cores can communicate! If you have seen the link to VR-Zone from the 1st post of this thread, you'll notice that there is a quadcore without (shared) L3 on the roadmap.

Obviously though, accessing shared data through RAM is nothing near the L3 performance.There is no shared data in RAM and in the L2 and L1 of K8 and K10. Sharing data != core-to-core communication.

The logic is different- it can't possibly be the same, but I was implying that you do little help to use L3 in a dualcore design that does not save space when L2 brings little penalties overall in a DC (not even power usage or heat is that big of an issue relatively speaking)
1) The L3 has higher impact on a dualcore than on a quadcore.
2) The L2 brings only benefits.


What would the design be, pray tell, if it's not a derivative of K10(.5)? A cache enhanced Brisbane? :)It can be enhanced K8 or simplified K10/K10.5.

BTW K8 cores communicate via the Crossbar. That is not true. The cores on K8 communicate via the RAM.

[freeloader]

It's all good as long as I can get a Socket 1207 FX based on Deneb.

[The Coolest]

That is not true. The cores on K8 communicate via the RAM.

Then what is the Crossbar for in them?

[gOJDO]

Then what is the Crossbar for in them?The K8 crossbar connects the resources on the chip, but the core-to-core communication is happening via the RAM.

The L1 and the L2 on the K8 are exclusive and that means that there is no other copy of the L1 and L2 data in another core, another CPU or RAM at the same time.

When the 2 cores on the K8 dualcore are communicating, the first core(the data sender) is always doing a write-back to RAM, thus removing the data from its L2. Then the second core (the data receiver) is copying the data from the RAM to its L2 and at the same time the data is removed from the RAM(no other copy of the data exists). In this data transactions the crossbar is used to connect the IMC with the L2 of the cores, but it is not conecting the cores directly.

The core-to-core communication on the K10 is happening via the shared L3 and in this case also there is no direct core-to-core communication via the crossbar.

[Kuroimaho]

Seems there is a TDP drop going from AM2+ to AM3? Either that or they are releasing slower models of Deneb on AM3 initially in February, then moving onto the faster AM2+ speeds in March?

The AM3 cpus will come with new power saving features which of course only work in Am3 boards that might be why those come with lower TDP

[Shintai]

Seems there is a TDP drop going from AM2+ to AM3? Either that or they are releasing slower models of Deneb on AM3 initially in February, then moving onto the faster AM2+ speeds in March?

They seem the same to me. 125W aswell as 95W. I would rather guess that its just launching with the lower speed before the higher in march.

[Sumanji]

The AM3 cpus will come with new power saving features which of course only work in Am3 boards that might be why those come with lower TDP

Aha good point :)

I was going to do an AM2+ Deneb build, but now I will wait for AM3 since it's only March.. and if AM3 sucks then I can get Nehalem with some cheap(er) DDR3 :D

[gOJDO]

Deneb is not going to suck. It will be a nice and fast CPU, but it won't be a match for Nehalem. According to AMD roadmap we should expect a 3GHz Deneb DDR2/DD3 in January/February 2009. Its success depends of its price. Also you can consider on a cheap Yorkfield/Kentsfield. Kentsfield will compete against Deneb in performance(IPC and clock - wise), while Yorkfield in both performance and energy efficiency. It is not yet certain if Deneb based system will be less power hungry than a Yorkfield based one, but according to some power consumption tests done by individuals on a Deneb ES, Deneb is a very energy efficient CPU.

[@@@@]

This road map is closer to the specifications that is floating around this has a higher chance of probability

[metro.cl]

All this has already been exposed ;)

[HKPolice]

3Ghz Denab vs 3.2Ghz Nehalem.

Round 1: FIGHT
Nehalem WINS! Flawless Victory!

[Trunks]

3Ghz Denab vs 3.2Ghz Nehalem.

Round 1: FIGHT
Nehalem WINS! Flawless Victory!

and your point is...? :rolleyes:

[SparkyJJO]

3Ghz Denab vs 3.2Ghz Nehalem.

Round 1: FIGHT
Nehalem WINS! Flawless Victory!

And the point of this post is....? :rolleyes:

Worthless post, this thread has absolutely nothing to do with nehalem :down:

[Sumanji]

If Deneb can clock to 4GHz with ease and at least beat Yorkfield's IPC, then we have a ball game...

[MrMojoZ]

Guys, you know good and well that AMD threads aren't allowed without some idiot posting un-related Intel stuff. I'm sure he was just making sure that the thread wasn't closed for violating that rule.

[YukonTrooper]

funny nobody mentioned/noticed the change in dualcore... its no longer a k10 but its actually an improved brisbane k8 on 45nm with new mem controller and 1mb cache/core

small die, low cost.
Wow. So AMD's 2009 dual-core technology will possibly be slower than Intel's 2006 dual-core technology? Say it ain't so.

[informal]

Wow. So AMD's 2009 dual-core technology will possibly be slower than Intel's 2006 dual-core technology? Say it ain't so.

It ain't so since it will not be 45nm Brisbane derivative but a K10.5 with 1MB of L2 per core and no L3.

[vengance_01]

For AMD, its not about getting the crown back, but making a chip that OEM's want and can use, and something that has high yields and is cheap to make. They need to become profitable first, then they can worry about Intel.

[Extelleron]

Wow. So AMD's 2009 dual-core technology will possibly be slower than Intel's 2006 dual-core technology? Say it ain't so.

I don't know where this rumor started, but Regor is almost certainly K10 based. With the large L2 and no L3 (which makes no sense for a dual core and increases memory latency) I think that Regor will perform well.

[Hornet331]

I don't know where this rumor started, but Regor is almost certainly K10 based. With the large L2 and no L3 (which makes no sense for a dual core and increases memory latency) I think that Regor will perform well.

we need to wait for numbers before we can judge on this. :up:

[Cooper]

it's hard for me to understand why people are still waiting for miracles from AMD. Although AMD does and will make good products for their price and be very competitive on the market...as long as marketing and sales departments will stop sitting on their butts...
For XS it's definitely not an argument but for the 99% of the market it is and I truly hope AMD will regain the market share of the past and will keep on going.

[G0ldBr1ck]

it's hard for me to understand why people are still waiting for miracles from AMD. Although AMD does and will make good products for their price and be very competitive on the market...as long as marketing and sales departments will stop sitting on their butts...
For XS it's definitely not an argument but for the 99% of the market it is and I truly hope AMD will regain the market share of the past and will keep on going.

Are you saying it can never happen?

[Jaivan]

Wonder what the Deneb FX will be like and if they are going to offer anything special over the black edition chips?

Hopfully it'll come with the rumored 4GHZ clock speed lol.

[JumpingJack]

kuma are disabled agena and toliman's, so yes they exist :)

I would love to get my hands on a Kuma then, and pry off the IHS ... because it is very unlikely AMD would go to market with a 283 mm^2 dual core CPU in this current market environment. They would be much better off taping out a specific mask for 1/2 the die size.

[JumpingJack]

it's hard for me to understand why people are still waiting for miracles from AMD. Although AMD does and will make good products for their price and be very competitive on the market...as long as marketing and sales departments will stop sitting on their butts...
For XS it's definitely not an argument but for the 99% of the market it is and I truly hope AMD will regain the market share of the past and will keep on going.

AMD doesn't really need any miracles technologically (they do financially). What they do need to do is simply keep up within where they are performance wise. Their argument that they can make a good business in the mainstream is a great one.

AMD is AMD's own worst enemy at the moment though ... over the past two years, they have slipped back into the historical pattern than kept the enigma of a second runner up supplier -- K7, K8 earned them hard fought credibility that they could be a first class supplier.... they lost some of that with K10...

Execution is key, and the recent performance of the ATI portion of the business is very encouraging. The real test is 45 nm ... I don't think the rumor mill -- Deneb in Jan 8, 09 -- assuming the rumor is true, is that big of a deal (other than they lose the Xmas sale opportunities). But if they don't deliver 45 nm into server in reasonable volume by end of year, this will hurt... not because they don't have product to sell, but they will likely have spent their last 5 bucks of credibility with investors and customers.


Jack

[gOJDO]

But if they don't deliver 45 nm into server in reasonable volume by end of year, this will hurt... not because they don't have product to sell, but they will likely have spent their last 5 bucks of credibility with investors and customers.
That's right Jack. I think that AMD won't scrue up this round again. They are not talking BS this time. No "Shanghai will outperform Intel offerings in various workloads by 40%", no bold claims, no 4GHz demonstrations on another planet, no clowns like Henri Rirchards BS-ing around with a "native" nonfunctional CPU in his hand.

Upon the K10 launch their marketing department was worse than Intel's in the Pentium 4 days. Thanks god, they have learned the lesson and are being quiet now. I wish them a good luck and I wish us a fast and OC-able Denebs. Kentsfield and Yorkfield are no more interesting to play with. :)

[hollo]

and your point is...? :rolleyes:And the point of this post is....? :rolleyes:

Worthless post, this thread has absolutely nothing to do with nehalem :down:Guys, you know good and well that AMD threads aren't allowed without some idiot posting un-related Intel stuff. I'm sure he was just making sure that the thread wasn't closed for violating that rule.heaven forbid someone compare Intel and AMD in a thread on XS... :rolleyes:I don't know where this rumor started, but Regor is almost certainly K10 based. With the large L2 and no L3 (which makes no sense for a dual core and increases memory latency) I think that Regor will perform well.nope, data pulled from memory doesn't need to 'pass through' the l3

[insurgent]

heaven forbid someone compare Intel and AMD in a thread on XS... :rolleyes:

Did you see his comment as an invitation to an "intelligent discussion"? Heaven forbid flame baiting is called out in this forum.

[Nedjo]

That's right Jack. I think that AMD won't scrue up this round again. They are not talking BS this time. No "Shanghai will outperform Intel offerings in various workloads by 40%", no bold claims, no 4GHz demonstrations on another planet, no clowns like Henri Rirchards BS-ing around with a "native" nonfunctional CPU in his hand.

Upon the K10 launch their marketing department was worse than Intel's in the Pentium 4 days. Thanks god, they have learned the lesson and are being quiet now. I wish them a good luck and I wish us a fast and OC-able Denebs. Kentsfield and Yorkfield are no more interesting to play with. :)
I agree with the opinion that it's priority to go first with Server part 'cos market is entering in the new cycle of big IT equipment acquisition - servers on the first place. And in this round more then ever Virtualization will play big role upon decision making... Q4 is critical 'cos that's the time when all starts. Companies are getting clear picture of how much they'll be able to spend on IT department renewal, and will make purchasing plans based on that and based on what server guys have to offer...

On the other hand due to bunch of different things going on in consumer life (gas price, food price, housing...) this year more then ever consumer will be extremely price conscious, and AMD has already low enough price to be desirable buy for price sensitive average Joe...

[gOJDO]

We'll have to wait and see about the pricing. Intel also have interesting prices. Competition is nice.

[hollo]

Did you see his comment as an invitation to an "intelligent discussion"? Heaven forbid flame baiting is called out in this forum.nehalem will rape deneb

[insurgent]

nehalem will rape deneb

:confused: Is this supposed to prove your wit? It's failing big time :p:

[Rammsteiner]

Are you saying it can never happen?
Im more wondering whether it's needed to be honest. All those people crapping over Phenom... Phenom had its issues at launch with TLB bug and malfunctioning southbridge.

Both have been fixed now, but due to mainly that southbridge enthusiasts either were left at low clockspeeds waiting for a fix (which actually did take quite a time though), enthusiasts not having the money to upgrade for every fart might have chosen for a C2Q instead.

However it's quite shown K10 is going a lot stronger now, but at some point a certain CPU, or any product for that matter, gets black listed no matter it got fixed.

I think the 2nd round only starts when Deneb is launched and people can drop it in a complete fixed mobo (aka SB750). But I think for this 1st round, Agena, there's no hope no matter how good it actually is doing. But to say we're hoping for miracles, I dont think they even need one to be very honest.

heaven forbid someone compare Intel and AMD in a thread on XS... :rolleyes:nope, data pulled from memory doesn't need to 'pass through' the l3
nehalem will rape deneb
Maybe you'd like to use a dictionary next time.
First off, who cares about 'heaven' or anything related to that.
Secondly, I think it's quite epic to use the word 'rape' in computer hardware related fora, let alone to think there might be people out there who got raped by those wonderfull 'heaven people':shakes:
Third, chose your words better, Bloomfield is most likely to own Deneb, but that's about it thus far.

Let me ask this other question, what is the point of comparing AMD and Intel in a leaked CPU roadmap thread, which has been known already in the first place? With only ES previews thus far!? wut:confused::rofl:. Besides that, Bloomfield is a server aimed platform, now it can be me being retarded, but how should K10 offer Bloomfield resistance in the first place. Barcelona pretty much owns a QX9650, so what:shrug:

[c931]

The L1 and the L2 on the K8 are exclusive and that means that there is no other copy of the L1 and L2 data in another core, another CPU or RAM at the same time.
It means no duplicated data between L1 and L2, nothing more. Of course both caches contain copies of RAM-data (+other data). Otherwise reading the same data 100 times in a row would require 100 memory accesses.

And there are copies between both cpu-local caches. Example: cpu0 read, cpu1 read from the same address. Now the cache line is in both cpu-local caches and both copies marked S for "shared" in the MOESI cache coherence protocol.

When the 2 cores on the K8 dualcore are communicating, the first core(the data sender) is always doing a write-back to RAM, thus removing the data from its L2.
No and no. cpu0 modifies+writes some data, cache line is O-state. cpu1 can read the line via HT from cpu0s cache. The program looks like: cpu0 write mem, cpu1 read mem but the data is not really transfered via slow memory.

[Hornet331]

Let me ask this other question, what is the point of comparing AMD and Intel in a leaked CPU roadmap thread, which has been known already in the first place? With only ES previews thus far!? wut:confused::rofl:. Besides that, Bloomfield is a server aimed platform, now it can be me being retarded, but how should K10 offer Bloomfield resistance in the first place. Barcelona pretty much is owned by a QX9650, so what:shrug:

fixed :p:

[JumpingJack]

No and no. cpu0 modifies+writes some data, cache line is O-state. cpu1 can read the line via HT from cpu0s cache. The program looks like: cpu0 write mem, cpu1 read mem but the data is not really transfered via slow memory.

That is the way I have always understood it to work too, but Xbitlabs determined differently, or the crossbar (not the HT) has much more latency than what is reasonable:
http://www.xbitlabs.com/articles/cpu/display/dualcore-dtr-analysis.html

The results aren’t encouraging. The data transfer latency has become a little higher, but the overall picture has remained the same. The second thread’s data access latency is too high for this thread to be possibly reading directly from the first core’s cache. When randomly reading the modified data (Picture 4), there’s a small growth of data transfer latency for data blocks smaller than 512MB which may be due to the necessity to copy the modified cache lines into system RAM.

EDIT: Just another excerpt from the same article:
So, I have to state that I can’t find any indication of direct data transfers from one execution core to another in the Athlon 64 X2 processor. According to my tests, the most recent copy of data is always read from system RAM. This must be a limitation of the MOESI protocol implementation. The following seems to happen when data are accessed: on receiving a read request probe read that the second core puts on the system bus, the first core performs a write-back of the modified cache line into memory. After this write or at the same time with it, the requested line is transferred to the second core. If the data in the first core’s cache haven’t been modified, they are read from system RAM. Why is there no direct transfer between the cores via the crossbar switch? Ask AMD’s engineers about that! :)

It could be that the crossbar is just simply very high latency, but this does not make any sense.

Of course this is between dual core, I wish xbit would do the same analysis on quads to see the difference.

[Rammsteiner]

fixed :p:
You basicly think 32 Barcelona cores are going to do worse than a QX9650? That's a bit... sad.. really.

I admit it's a stupid comparison, but just as stupid as Bloomfield vs K10. Although Bloomfield has a little purpose still on for desktop usage, Lynnfield is the 'real' desktop variant. It's almost the same as comparing cheaper ST vs, well, lets say the new Kuma CPU for that matter.

And we all know by now that thus far it seems that Bloomfield is going to rock, well, numbers wise. But that's not K10's competitor, not even close. It's real competitor is Barcelona, we'll have to wait how it's going to do vs Shanghai.

Spoken about that, I'd like to see a comparison of x core Barcelona vs x core Shangai:D But I think to get full potential from Shanghai we might have to wait a bit longer for the newer server chipsets:rolleyes:

[JumpingJack]

I admit it's a stupid comparison, but just as stupid as Bloomfield vs K10. Although Bloomfield has a little purpose still on for desktop usage, Lynnfield is the 'real' desktop variant. It's almost the same as comparing cheaper ST vs, well, lets say the new Kuma CPU for that matter.


Bloomfield is to desktop as Agena is to desktop. AMD designed a server part in both K8, and K10, then repackaged it to desktop. Nehalem address server shortcomings in the Intel platform, but will now form the basis for the desktop versions.

Lynnsfield (and this is my opinion) demonstrates the utility of the modular design approach (something AMD originally touted, but has not yet delivered). In this case, the processor can be tailored for a market segment, in this case the mainstream client over performance.

Most all roadmaps from AMD and Intel show the DT segment, sub-segmented if you will, the very top is performance (the Extreme/FX verions, and top bin locked mutliplier), the mainstream (next few bins), and value (semprons, celerons, pentium brand now).

So, in a way, both AMD and Intel are launching their new processors correctly AMD is going for server, Intel is going for performance DT -- both low volume segments overall, with good margins. Makes sense, new products typically take time to ramp and build inventory, so I would think a company would want to avoid over stimulating demand by producing brands into the high volume segments.

Jack

[informal]

Lynnsfield (and this is my opinion) demonstrates the utility of the modular design approach (something AMD originally touted, but has not yet delivered). In this case, the processor can be tailored for a market segment, in this case the mainstream client over performance.


AMD did this "tailoring" already,with Griffin.They modified the K8 chip making it more "mobile friendly" by using modular approach(replacing/making a new IMC with much better power management and adding more power planes ,for each core too,among other stuff).

[Rammsteiner]

JJ, I think that I more or less meant that. Bloomfield is a server CPU but can be used as desktop variant too. Maybe a bit comparable with FX-51/53 on skt 940? Or maybe better, compared with FX-53~57 on skt 939 (which was basicly from top binned Opteron chips).

It still does not change that Bloomfield is not the competitor for K10 though. At least, from what I conclude thus far from both ES Deneb and Bloomfield previews and pricings.

[JumpingJack]

JJ, I think that I more or less meant that. Bloomfield is a server CPU but can be used as desktop variant too. Maybe a bit comparable with FX-51/53 on skt 940? Or maybe better, compared with FX-53~57 on skt 939 (which was basicly from top binned Opteron chips).

It still does not change that Bloomfield is not the competitor for K10 though. At least, from what I conclude thus far from both ES Deneb and Bloomfield previews and pricings.

Ahhh, I may have read too far into it then... however, weren't the FX cpus and the A64 and X2s exactly the same, just lower binned and locked multipliers? AMD doesn't maintain a different architecture for even Sempron's compared to their top bin DTs. The same with current core Celeron's and Pentium's, they are still the core microachitecture just clocked and branded low end.

I have always found it interesting how AMD and Intel interact. By this I mean, when one turns left the other turns right (at the technological level anyway). I wonder if there is a small wiff of pride swirling in the minds of the technology deciders when they map out plans and designs :) ....

Intel (late 1990's) to 2006 more or less tried to maintain 3 different designs for the 3 different segments, then took mobile and pushed it to the common architecture. AMD, on the other hand, started with a very server centric approach, then waterfalled it down to desktop and attempted mobile (they had a hard time getting there and let Intel dominate mobile). Look at how it panned out... Intel was dominant in mobile 2003-2005/6ish, AMD was dominant in server 2003-2006... I would call them about even in server today -- AMD dominants some workloads, Intel dominates others.

I agree with you that AMD's marketing strategy should not be to dominate Bloomsfield... and I think that is absolutely the right approach... why?

Intel is transitioning the fundamental platform architecture, which means the adoption rate will be much slower. The place where AMD can compete will be in the Kentsfield/Yorksfield type product area as that will still be the majority of the CPUs Intel will be pushing for 6 mo to a yr.

On the flip side, I think Intel was also very smart in how they decided to make this transition ... they had to do it from a position of strength so that older product could compete well, while the adoption took place. No one, not Intel not AMD, believed Intel could stay with the aging FSB forever, everyone expected them to eventually integrate the mem controller and go point to point in some fashion, the question for Intel was really timing.
My opinion anyway.


Jack

[Shadowmage]

No one, not Intel not AMD, believed Intel could stay with the aging FSB forever, everyone expected them to eventually integrate the mem controller and go point to point in some fashion, the question for Intel was really timing.

Ahem... except for certain Intel fanboys :p

[JumpingJack]

AMD did this "tailoring" already,with Griffin.They modified the K8 chip making it more "mobile friendly" by using modular approach(replacing/making a new IMC with much better power management and adding more power planes ,for each core too,among other stuff).

This is a bit different than a modular approach. AMD reworked the IMC, some power saving features, etc... it is still K8 with all the basic blocks. But did they add a block here, or remove a block there? No this is not modular, this is just straight up design around what you already have.

You can divide the blocks of any processor up, but a modular design is adding or removing each block to make a new device tailored for a specific purpose. Cell, for example, is a good modular design -- 8 cores, it can work with up to 6, and they can add or subtract cores to address different performance segments. I take exception to Intel's claim that Nehalem is the first modular design -- Cell is modular as well ... however, if they said first modular x86 design, well that is word play to be technically correct.

Intel approached nehalem with a modular design .. I can dig up the slides, they are somewhere on the WWW :) ... what this does, in order to produce a new product, is eliminates the necessity to redesign the basic blocks (core, IMC, cache, GPU - eventually, for mobile - PCIe) ... Add an extra channel of memory for 3 channels instead of two, or two more cores in stead of 4, or add another chunk of L3 cache (this really isn't 'modular' per se I suppose), or plug in a PCIe port... then wire them up and manufacture. Just like lego blocks.... this is novel if it works -- right now, Nehalem quads with 2 channels DDR3 is the rev 0 iteration. This approach allows market specific productization without the overhead of rewriting the logic core blocks (as AMD did with Griffin).

AMD originally touted it when they pitched their roadmaps to investors and technologist around the initial Barcelona disclosures -- we don't here them talk about it any more and I have not seen them actually implement it.

Jack

[informal]

This is a bit different than a modular approach. AMD reworked the IMC, some power saving features, etc... it is still K8 with all the basic blocks. But did they add a block here, or remove a block there? No this is not modular, this is just straight up design around what you already have.

You can divide the blocks of any processor up, but a modular design is adding or removing each block to make a new device tailored for a specific purpose. Cell, for example, is a good modular design -- 8 cores, it can work with up to 6, and they can add or subtract cores to address different performance segments. I take exception to Intel's claim that Nehalem is the first modular design -- Cell is modular as well ... however, if they said first modular x86 design, well that is word play to be technically correct.

Intel approached nehalem with a modular design .. I can dig up the slides, they are somewhere on the WWW :) ... what this does, in order to produce a new product, is eliminates the necessity to redesign the basic blocks (core, IMC, cache, GPU - eventually, for mobile - PCIe) ... Add an extra channel of memory for 3 channels instead of two, or two more cores in stead of 4, or add another chunk of L3 cache (this really isn't 'modular' per se I suppose), or plug in a PCIe port... then wire them up and manufacture. Just like lego blocks.... this is novel if it works -- right now, Nehalem quads with 2 channels DDR3 is the rev 0 iteration. This approach allows market specific productization without the overhead of rewriting the logic core blocks (as AMD did with Griffin).

AMD originally touted it when they pitched their roadmaps to investors and technologist around the initial Barcelona disclosures -- we don't here them talk about it any more and I have not seen them actually implement it.

Jack

Adding in a PCI-e controller as opposed to redesigning IMC is not an easier task at all.They practically used a proven design(K8) reworked it a bit and made a better mobile chip out of it(add in one -better - feature and replace the older one,an IMC in this case;add in more PLLs and control the core/uncore power mana. in much better way).

Also ,all the things you mentioned about Nehalem "modular-like" features apply to Barcelona too(apart from PCI-e integration).You will have 2 core version of Deneb(Regor with no L3),you will have 4 core Propus with no L3(around 160-170mm2),you will have 6 core native variation,you see the modular L3 cache approach in terms of size with K10 and K10.5(doesn't matter if it's 65nm->45nm,it's basically the same design).AMD doesn't use 3 channel IMC so they can't disable one channel,but they will support the MCMing of the K10.5 cores and scale them up to 12 cores which is the simplest example possible how with almost zero added cost you scale up one uarch. and double perf./watt. AMD's slide actually covered all the above: add cores/drop cores ,add L3 cache/loose L3 cache,couple cores in MCM,add GPU(Fusion,next year),add PCI-e(will come in future) etc.

[JumpingJack]

Adding in a PCI-e controller as opposed to redesigning IMC is not an easier task at all.They practically used a proven design(K8) reworked it a bit and made a better mobile chip out of it(add in one -better - feature and replace the older one,an IMC in this case;add in more PLLs and control the core/uncore power mana. in much better way).

Also ,all the things you mentioned about Nehalem "modular-like" features apply to Barcelona too(apart from PCI-e integration).You will have 2 core version of Deneb(Regor with no L3),you will have 4 core Propus with no L3(around 160-170mm2),you will have 6 core native variation,you see the modular L3 cache approach in terms of size with K10 and K10.5(doesn't matter if it's 65nm->45nm,it's basically the same design).AMD doesn't use 3 channel IMC so they can't disable one channel,but they will support the MCMing of the K10.5 cores and scale them up to 12 cores which is the simplest example possible how with almost zero added cost you scale up one uarch. and double perf./watt. AMD's slide actually covered all the above: add cores/drop cores ,add L3 cache/loose L3 cache,couple cores in MCM,add GPU(Fusion,next year),add PCI-e(will come in future) etc.

Ok, so when we see Barcelona add another channel of DDR2, or integrate the PCIe, or put in more cores, and bring it out at 65 nm, I will call it modular. (We have yet to see a 2 core chop from Barcelona BTW). But nothing about Barcelona is a modular design, or dynamically scalable. This is why I also said, until we see the Nehalem variants, we won't know if it is really a successful approach, i.e. I meant to imply that when I said "this is novel if it works" ...

AMD may make it there with 45 nm technology, but i doubt you will see even a core chip from Barcelona. Simply disabling a channel is not modular either, if I read Intel correctly they will physically add or remove what they need ... die size and layout will tell us if this is true.

MCMing two die is not modular designing either. Oddly, AMD is embracing the sandwich approach where in the past they made so much fun of it as being inadequate.

jack

[informal]

Ok, so when we see Barcelona add another channel of DDR2, or integrate the PCIe, or put in more cores, and bring it out at 65 nm, I will call it modular. (We have yet to see a 2 core chop from Barcelona BTW). But nothing about Barcelona is a modular design, or dynamically scalable. This is why I also said, until we see the Nehalem variants, we won't know if it is really a successful approach, i.e. I meant to imply that when I said "this is novel if it works" ...

Being modular is not restricted to only one node and you should know that... Modular design is meant to bring the best results (seen from one uarch. POV) exactly on process node transitions.Shanghai is Barcelona shrunk and slightly tweaked.So whenever you say Shanghai/Deneb you practically say Barcelona/Phenom (in terms of uarchitecure).Barcelona will not add another channel since it will not need it.DDR3 will be a sort of addition and will be perfectly enough for 4/6 cores-so there's even better example then basic switch off of one channel since you get more functionality and retain backward support ,which Nehalem doesn't do with DDR2.
Taking K10.5 core to a new socket in 2010 will bring another supporting memory standard.

Everything from Barcelona is modular,just as is with Nehalem.It is only for the fact that Barcelona wasn't made @ 45nm first for us not to see bigger L3 cache,less cores/more cores.Dual core "chop" we didn't see since they lost one quarter on TLB blunder and that you can't make up easily.It's simple matter of physics and engineering and what you can/can't do at one moment.

Nehalem will be made on 45nm process and from basic uarch. POV is Shanghai copy/equivalent.It only took them 5 years to make it happen and it's coming out at the same time or near the same time of Shanghai(server part).So anything intel can do with Nehalem ,AMD will be doing with K10.5(K10@45nm).
More L3/no L3,native dual core(cheap/rel. fast),new mobile design with Fusion(clear modular approach with GPU int.),more cores (Istanbul native 6 core part),more ores with Magny Cours(2x 6 cores) etc.

[JumpingJack]

Being modular is not restricted to only one node and you should know that... Modular design is meant to bring the best results (seen from one uarch. POV) exactly on process node transitions.Shanghai is Barcelona shrunk and slightly tweaked.So whenever you say Shanghai/Deneb you practically say Barcelona/Phenom (in terms of uarchitecure).Barcelona will not add another channel since it will not need it.DDR3 will be a sort of addition and will be perfectly enough for 4/6 cores-so there's even better example then basic switch off of one channel since you get more functionality and retain backward support ,which Nehalem doesn't do with DDR2.
Taking K10.5 core to a new socket in 2010 will bring another supporting memory standard.

Everything from Barcelona is modular,just as is with Nehalem.It is only for the fact that Barcelona wasn't made @ 45nm first for us not to see bigger L3 cache,less cores/more cores.Dual core "chop" we didn't see since they lost one quarter on TLB blunder and that you can't make up easily.It's simple matter of physics and engineering and what you can/can't do at one moment.

Nehalem will be made on 45nm process and from basic uarch. POV is Shanghai copy/equivalent.It only took them 5 years to make it happen and it's coming out at the same time or near the same time of Shanghai(server part).So anything intel can do with Nehalem ,AMD will be doing with K10.5(K10@45nm).
More L3/no L3,native dual core(cheap/rel. fast),new mobile design with Fusion(clear modular approach with GPU int.),more cores (Istanbul native 6 core part),more ores with Magny Cours(2x 6 cores) etc.

This is true .. it is not node specific it is design specific -- barcelona design came in at 65 nm... if it were modular as modular implies simpler turn around on new products, we should be seeing different variations of that product within the same node, should we not? Kuma was rumored/roadmapped to arrive Q4 2007, then revised to Q1 2008, and we still haven't seen it... very indicative if a new design which goes against a modular concept does it not?

If a 'chop' were so easy, then AMD should be able to simply tape out a 2 core mask and go from there ... yet it is over a year late.

I did not say AMD was not going to do the same thing, nor that they were incapable, I just haven't seen them deliver it yet... same can be said of Intel to this point, Intel simply says nehalem is modular, until they launch product variations using the 'rubber' stamp cores, memory channels, yada yada, it is not proven. Hence, "novel if it works' statement.

Second, you miss the point of adding or subtracting channels... a modular approach enables this... If intel launches a 2 channel DDR3 chip in to the market and the die shot reveals only two physcial channels, this is modular, meaning they targeted the device for a purposes, added what was needed and saved die space. This is different than what you are arguing. Having a core, a L3 cache, an IMC, a HT pad .. these are all blocks laid out on the die.... adding and subtracting them at will ... that's modular.

Jack

[Rammsteiner]

Ahhh, I may have read too far into it then... however, weren't the FX cpus and the A64 and X2s exactly the same, just lower binned and locked multipliers? AMD doesn't maintain a different architecture for even Sempron's compared to their top bin DTs. The same with current core Celeron's and Pentium's, they are still the core microachitecture just clocked and branded low end.
Now you say, I think I might have pulled the wrong example for FX-53~57 on skt 939 since San Diego was basicly the very same. I guess FX-51/53 on 940 is a better example (server platform being used as enthusiast only). However better they got rid of that sooner than later since A64 3400+ already let the FX-51 eat lots of dust regarding price/performance.

On the flip side, I think Intel was also very smart in how they decided to make this transition ... they had to do it from a position of strength so that older product could compete well, while the adoption took place. No one, not Intel not AMD, believed Intel could stay with the aging FSB forever, everyone expected them to eventually integrate the mem controller and go point to point in some fashion, the question for Intel was really timing.
My opinion anyway.


Jack
Well, I share that opinion;) That's what I found so impressive about Intel and the whole Nehalem thing. In the end they did barely anything with Kentsfield and not all that much with Yorkfield either. They simply could afford to release it at higher clocks to keep everyone happy, do a few price drops now and then since you cant ask the same price for a certain product for more than a year (apart from nVidia then:p:) and release a slightly higher clocked CPU. At the end they release a few new steppings/higher clocked CPU's on a killer architecture to keep a buffer untill Nehalem. It fits all right in:cool:.

But well, both AMD and Intel had those moments, both had the opposite of it. Intel couldnt do anything else but watch AMD going with the crown in K8 days, AMD couldnt do anything else then seeing Intel taking it back in Conroe days. I love to see those things happening.

On the otherhand, I wish it didnt, it only makes certain people go nuts and call others names:down: But if that didnt happen with hardware business, it would have gone over to idealogy/religion. People will always have something to discuss:(

[informal]

This is true .. it is not node specific, but if it were modular as modular implies simple new products, we should be seeing different variations of that product within the same node, should we not? Kuma was rumored/roadmapped to arrive Q4 2007, then revised to Q1 2008, and we still haven't seen it... very indicative if a new design which goes against a modular concept does it not?

I did not say AMD was not going to do the same thing, nor that they were incapable, I just haven't seen them deliver it yet... same can be said of Intel to this point, Intel simply says nehalem is modular, until they launch product variations using the 'rubber' stamp cores, memory channels, yada yada, it is not proven. Hence, "novel if it works' statement.

Second, you miss the point of adding or subtracting channels... a modular approach enables this... If intel launches a 2 channel DDR3 chip inot the market and the die shot reveals only two physcial channels, this is modular, meaning they targeted the device, added what was needed and saved die space. This is different than what you are arguing.

Jack
I addressed you complaint with K10 @ 65nm dual core previously.It's all about time and what they could do.They messed up with initial K10 and it cost them dearly.They delayed/postponed anything that was planned for B2 and switched to B3.This led to delay of dual core variant if not canceling it altogether due to(duh) obvious reason named 45nm process node starting(why focus on dual core K10 @ 65nm when you will have 4 core Propus with the same die size;why focus on dual core K10 @ 65nm when you can have a Regor one that is 2x smaller).I'm not sure about KUma,but i suppose there is a slight chance it is actually a real dual core(not disabled quad).Slight as being very slight.

As for your 3 channel remark,i would really like to see intel go trough the new mask process for a "special" quad core/dual core chip with only 2 channel support in IMC(my guess is they won't do that).The point of the 2/3 channel is not saving the die area as you said(which could be trivial ,just think about it...),but a cost of traces to memory on the PCB.Boards sporting 2 channels will cost a lot less... Oh,btw,if AMD would introduce an only-DDR3 IMC that would cut the die area compared to the DDR3/DDR2 one,would that be a modular approach?And isn't it a modular already since the "original" K10 supports only DDR2?Being done @ 45nm doesn't mean it's "not fair" to take it in consideration since it's the same uarchitecture after all.

[JumpingJack]

I addressed you complaint with K10 @ 65nm dual core previously. It's all about time and what they could do.
Well, I am not complaining, just making an observation. This is also where I think you are wrong. Modular design implies easy, no hassle product development, if Barcelona were modular as you seem to think the way modularity works, we should have seen Kuma way way before now.

They messed up with initial K10 and it cost them dearly.They delayed/postponed anything that was planned for B2 and switched to B3.This led to delay of dual core variant if not canceling it altogether due to(duh) obvious reason named 45nm process node starting(why focus on dual core K10 @ 65nm when you will have 4 core Propus with the same die size;why focus on dual core K10 @ 65nm when you can have a Regor one that is 2x smaller).I'm not sure about KUma,but i suppose there is a slight chance it is actually a real dual core(not disabled quad).Slight as being very slight.

This I do not disagree with -- the K10 launch was not their best moment. Not only did this make the late to the quad core game, but as you say -- impacted a much need make over for the dual core line up. AMD's highest price dual core (quick glance at the Egg) is 139, this is a 3.2 GHz windsor (excess stock obviously, OEM) -- one at 109, all others below 100 ... Penryn has essentially pushed AMD down to the Celeron Sempron pricing levels of 2 years ago.

They really need(ed) Kuma to shore up the lower half of the lineup, they settled for Toliman, not nearly as cost effective. Sure focus on the 45 nm now... they have already suffered the damage by not having better competing dual cores for the last 2 years -- to the tune of several billion in the red.

As for your 3 channel remark,i would really like to see intel go trough the new mask process for a "special" quad core/dual core chip with only 2 channel support in IMC(my guess is they won't do that).The point of the 2/3 channel is not saving the die area as you said(which could be trivial ,just think about it...),but a cost of traces to memory on the PCB.Boards sporting 2 channels will cost a lot less... Oh,btw,if AMD would introduce an only-DDR3 IMC that would cut the die area compared to the DDR3/DDR2 one,would that be a modular approach?And isn't it a modular already since the "original" K10 supports only DDR2?Being done @ 45nm doesn't mean it's "not fair" to take it in consideration since it's the same uarchitecture after all.

Die area and yield is the fundamental driver of the economics of the industry. High end, higher margin parts will get the needed channels, the lower end mainstream parts which are less performance sensitve and more price sensitive will save that die area -- every mm^2 counts. I will be willing to bet you a voluntary year ban from the boards that this will be true, i.e. two channel variants of Nehalem will indeed have two physical channels.

On your second point.... DDR2/DDR3 are the same memory controller, they do not implement two different controllers to service two memories. DDR2/DDR3 are differentiated by voltage, latency... a DDR3 controller can handle DDR2 memory signaling not vice versa. Shanghia die shots will show this to... The primary difference between DDR2/DDR3 is voltage and clock speed, the reason to push one over the other is power and voltage, some termination and some logic that does self-calibrating.

Example: http://www.viragelogic.com/upload/documents/DS_0138_ASIP_MC_D23_A1_FINAL.pdf

Virage Logic’s Application Specific IP (ASIP) Intelli DDR2/3 1600Mbps Memory Controller is a flexible
and advanced solution for ASIC, System-on-Chip (SoC) and FPGA designers who need to achieve
excellent performance from their memory interface. The Intelli DDR2/3 Memory Controller supports
both the DDR2 and DDR3 standards

One controller to support both standards ...

[informal]

Well, I am not complaining, just making an observation. This is also where I think you are wrong. Modular design implies easy, no hassle product development, if Barcelona were modular as you seem to think the way modularity works, we should have seen Kuma way way before now.



This I do not disagree with -- the K10 launch was not their best moment. Not only did this make the late to the quad core game, but as you say -- impacted a much need make over for the dual core line up. AMD's highest price dual core (quick glance at the Egg) is 139, this is a 3.2 GHz windsor (excess stock obviously, OEM) -- one at 109, all others below 100 ... Penryn has essentially pushed AMD down to the Celeron Sempron pricing levels of 2 years ago.

They really need(ed) Kuma to shore up the lower half of the lineup, they settled for Toliman, not nearly as cost effective. Sure focus on the 45 nm now... they have already suffered the damage by not having better competing dual cores for the last 2 years -- to the tune of several billion in the red.



Die area and yield is the fundamental driver of the economics of the industry. High end, higher margin parts will get the needed channels, the lower end mainstream parts which are less performance sensitve and more price sensitive will save that die area -- every mm^2 counts. I will be willing to bet you a voluntary year ban from the boards that this will be true, i.e. two channel variants of Nehalem will indeed have two physical channels.

On your second point.... DDR2/DDR3 are the same memory controller, they do not implement two different controllers to service two memories. DDR2/DDR3 are differentiated by voltage, latency... a DDR3 controller can handle DDR2 memory signaling not vice versa. Shanghia die shots will show this to... The primary difference between DDR2/DDR3 is voltage and clock speed, the reason to push one over the other is power and voltage, some termination and some logic that does self-calibrating.

Example: http://www.viragelogic.com/upload/documents/DS_0138_ASIP_MC_D23_A1_FINAL.pdf



One controller to support both standards ...

They were late in the game since they wanted to produce a monolithic quad core on a 65nm process node.That's the thing intel decided not to do,and intel is primarily a manufacturing power house.

As for the Kuma/Toliman and the effects on the financials,i really doubt it had that much of effect.AMD's largest loss was the very quad core server parts(where the big money is),not the consumer parts.And your comment about "several billion in the red" has not much to do with K10 (it has to some extend,but not too much),but has a lot to do with the thing called credit.They used the loan to pay ATi,that's why they were in red,they borrowed a couple billion bucks...It's not pocket money you know...

Lastly,i know IM controller does work with both standards but it certainly does take some additional logic to support both standards.As for the 2/3 channel possibilities with Core i7,of course intel could make a special budget Core i7 model with "only" 2 channel support by design.I just said that it would be easier for them to do it the other way around at first.If it cuts the die area and they think it will pay off,no doubt they will do it,but it is yet to be seen.

[Monkeywoman]

instead of pointing at what AMD did wrong, what can AMD do right? Add more cache? decrease latencies? knowing Xtremesystems, i bet there are some AMD and Intel engineers that browse our forums for info and opinions on their product. let those AMD guys see what they should do. just saying since you guys knoe so much...

[YukonTrooper]

They should make their dual-cores faster than Intel's three year old dual-cores.

[Rammsteiner]

instead of pointing at what AMD did wrong, what can AMD do right? Add more cache? decrease latencies? knowing Xtremesystems, i bet there are some AMD and Intel engineers that browse our forums for info and opinions on their product. let those AMD guys see what they should do. just saying since you guys knoe so much...
I dont know really. AMD had pulled things in the past with an upgrade as Deneb would be for Agena.

But in the case of K10... AFAIK more L3 would help a little bit in anyway. If you only look at the differences of X4vsX3vsX2, you see that if L3 cache stays the same, performance goes up simply because the fewer cores have more L3 cache/core available.

Tweaking latencies etc always helps, that's no secret at all. However, this counts for caches as well of course:p: Also I dont think we should be looking in this as 'what AMD could do right', this counts just as hard for Intel and if either of them could inprove latencies/cahce, they certainly would do so;).

I do think that AMD should move at least to high/k and metal gates. If that move does not improve clock yields as it did for Intel, then at least it helps for their power consumption.

For the rest, I dont know. Just to get Intel involved in my post, Intel is moving to their first K10-like architecture. Apart from the issues with K10 at launch, but to 6 months later as well, K10 is good. But Intel used a complete other aproach for their CPU's. Yet people decided to go on a number-rage and crap over K10, but now Intel is about to launch Bloomfield the comparison comes at least a bit closer to reality. With the experience from Yorkfield/Kentsfield Intel still has an advantage if they would use those cores in native design, but on the otherhand, dont forget Intel simply has a killer architecture since Conroe. K8 wasnt bad at all, not at launch, not when Conroe was launched. K8 to K10 might have looked like an epic fail compared to P-D to Conroe and Conroe to K10, but I think that basicly Penryn to Nehalem might have a few drawbacks, but due to the huge buffer from the Penryn architecture it's less visible.

What do I mean with that? Well, Penryn really cant do a lot 'wrong' by anyone numbers wise (which counts for most of the time). Penryn has like the best improvements from the best single core designs now. So moving to a native quad core design plus adding the gains from an IMC only shows a very few drawbacks. K8 however was after Conroe not all that epic awesome anymore numbers wise. K10 being a native quad core with some improvements over K8, it did not catch up with Conroe a lot while Intel kept on improving its design while AMD was using their improvements from an IMC already, so they sort of 'used' their speed boost already to say it that way.

How this is going to continue, I dont know. I think no one else then AMD knows what they might have to change in their architecture to get better results. The fact is however that AMD has their experience now with both IMC's and native core designs and if there's some inefficient construction they might know about it now. If they do, only thing they've to ge sorted is to fix their single core architecture and put it in native design.

Or to go very short, AMD has the experience Intel doesnt, but so does Intel have their experience AMD doesnt have. And this sounds like a 'duh' moment, but I think this is the best way to illustrate what AMD should be looking into to get their K10(.5?) perform better.

Also Im PUI, so if there's lots of illogical sentences, dont blame me:p:

[JumpingJack]

Then what is the Crossbar for in them?

Snooping.

[JumpingJack]

They were late in the game since they wanted to produce a monolithic quad core on a 65nm process node.That's the thing intel decided not to do,and intel is primarily a manufacturing power house.
Yeah, the advantage (only advantage) the FSB has over AMD's direct connect, it was a quick and easy way to increase core count.


As for the Kuma/Toliman and the effects on the financials,i really doubt it had that much of effect.AMD's largest loss was the very quad core server parts(where the big money is),not the consumer parts.And your comment about "several billion in the red" has not much to do with K10 (it has to some extend,but not too much),but has a lot to do with the thing called credit.They used the loan to pay ATi,that's why they were in red,they borrowed a couple billion bucks...It's not pocket money you know...

Where I am coming from is that the result would have been better performing dual core parts, and they would be better able to shore up their ASPs based on the price/performance curve which Intel currently sets.

Lastly,i know IM controller does work with both standards but it certainly does take some additional logic to support both standards.As for the 2/3 channel possibilities with Core i7,of course intel could make a special budget Core i7 model with "only" 2 channel support by design.I just said that it would be easier for them to do it the other way around at first.If it cuts the die area and they think it will pay off,no doubt they will do it,but it is yet to be seen.

We just have a huge difference of understanding of what modularity means.... we will see in time I suppose.

Jack

[Rammsteiner]

They should make their dual-cores faster than Intel's three year old dual-cores.
Why, K8 was already faster in most apps than the whole P4 line anyway:rolleyes:

[JumpingJack]

instead of pointing at what AMD did wrong, what can AMD do right? Add more cache? decrease latencies? knowing Xtremesystems, i bet there are some AMD and Intel engineers that browse our forums for info and opinions on their product. let those AMD guys see what they should do. just saying since you guys knoe so much...

They are doing the right things now ... in my opinion. They are behind on a ground up redesign, so they pushed K10 as quickly as they could... got a healthy 10-15% improvement IPC, used that learning and larger cache to boost some more with Shanghai.

They need to at least maintain the status quo and give the A-team some time to do a major revision (Bulldozer?.. never clear on the details of what that really is).... nonetheless, AMD needs to do a few things to shore up the architecture.
- Better branch prediction -- intel just eats their lunch here.
- Strong prefetching -- again, Intel just eats their lunch.
- Their cache system is not too good either, need to improve that.
- Process Tech -- 65 nm will not be fondly remembered in my opinion, they need more headroom to get clock speeds up.

They have plenty of BW at the moment, so they need to refocus some effort on strengthening the core.

[YukonTrooper]

Why, K8 was already faster in most apps than the whole P4 line anyway:rolleyes:
Whoops. I meant AMD should make their dual-cores faster than Intel's two year old dual-cores. Meant the C2D's, not P4's. My bad. :)

[freeloader]

Whoops. I meant AMD should make their dual-cores faster than Intel's two year old dual-cores. Meant the C2D's, not P4's. My bad. :)

If not faster, at least within 2-3%. :D

[Rammsteiner]

If not faster, at least within 2-3%. :D
I think you might have missed my point:rolleyes:

[G0ldBr1ck]

This is kinda irrelevant to the subject but we still continue to refer to Deneb/Shanghai as K10.5. Since it seems that AMD is calling these the 11h family and K10 was 10h family, dont it seem logical that these will actualy be dubbed K11?

[informal]

This is kinda irrelevant to the subject but we still continue to refer to Deneb/Shanghai as K10.5. Since it seems that AMD is calling these the 11h family and K10 was 10h family, dont it seem logical that these will actualy be dubbed K11?

I'm not so sure AMD is calling Shanghai 11h,since 11h seems to be already taken by Griffin family of chips(specially modified Brisbanes with new IMC,HT3.0 support,2x L2 cache and much better power management).You can find Griffin tech data sheet at amd's website.

[Glow9]

Can someone explain the deal with Deneb and Shanghai? Is Shanghai a server chip? Cause I keep hearing it's suppose to rival nehalen yet it's not on this roadmap and was sposed to be coming out around same time as Deneb wasn't it?

[Epsilon84]

Yes, Shanghai is server and Deneb is desktop. They are essentially the same chip, so Shanghai would be Opteron K10.5 and Deneb Phenom K10.5. ;)

[Glow9]

Thanks for clearing that up. You know considering the pricing of both AMDs mobo lineup and Chips right now even if these new chips perform with say Q9550s and are cheaper I can't really see this as that bad. Considering how many people have AM2+ boards right now seems like a easy upgrade. But really how would I know I just hope they are better than e8400s/Q9300s

[Nedjo]

Can someone explain the deal with Deneb and Shanghai? Is Shanghai a server chip? Cause I keep hearing it's suppose to rival nehalen yet it's not on this roadmap and was sposed to be coming out around same time as Deneb wasn't it?
it's common misunderstanding that Deneb is suppose to rival Nehalem!

[Epsilon84]

Thanks for clearing that up. You know considering the pricing of both AMDs mobo lineup and Chips right now even if these new chips perform with say Q9550s and are cheaper I can't really see this as that bad. Considering how many people have AM2+ boards right now seems like a easy upgrade. But really how would I know I just hope they are better than e8400s/Q9300s

Early previews have Deneb roughly matching Kentsfield per clock so I doubt it would be better than Wolfdale/Yorkfield. That being said, it shouldn't be too far off the pace and if priced competitively should be a viable option for mainstream users.

AMD's biggest worry is if Intel decides to drastically cut Core 2 prices once Nehalem launches, since that would also mean lower prices for Deneb if they want to stay competitive in price/performance.

[STaRGaZeR]

it's common misunderstanding that Deneb is suppose to rival Nehalem!

So in your understanding what CPU Deneb is supposed to compete with?

[Nedjo]

So in your understanding what CPU Deneb is supposed to compete with?
to those CPUs with the same price!

[Hornet331]

to those CPUs with the same price!

so Q6600/Q6700 and Q8200/Q9300?

But wait they are all sub 200€ now, so that means no amd quads above 200€...

[Hell Hound]

Phenom Fx for 299 usd sound good to me,only if its 3.4 and faster than qx6850 or somthing like that.

[STaRGaZeR]

to those CPUs with the same price!

Names please ;)

[ryboto]

Names please ;)

How can he give names if he doesn't know the target price of the unreleased Deneb parts?

[duploxxx]

Early previews have Deneb roughly matching Kentsfield per clock so I doubt it would be better than Wolfdale/Yorkfield.

pls show the nice early previews from the first deneb that will be launched....

so Q6600/Q6700 and Q8200/Q9300?

But wait they are all sub 200€ now, so that means no amd quads above 200€...

nope its q9450-q9650 range....

[Hornet331]

pls show the nice early previews from the first deneb that will be launched....



nope its q9450-q9650 range....

So amd launches 3ghz plus and no sub 3ghz chips?

All we know for now deneb is at most on par with kentsfield, which still leaves yorkfield 5-10% faster then kentsfield/deneb.

With the Q9400 already screatching the 200€ mark, i still dont see how amd can ask more then 200€ for a proc, even when deneb is released with 3ghz stock. Plus it still is some time till we see deneb which will leave intel time to adjust prices accordingly.

I can draw this conclusin since most of the the time a 2,66ghz Q9450 is on par with the "old" QX6850. (http://techreport.com/articles.x/14573/1) Sometimes the QX6850 wins, sometimes the Q9450.

For myself i would like to see that amd has a processor that more worth then 200€, but for what i know today that ain't gonna happen.

[STaRGaZeR]

How can he give names if he doesn't know the target price of the unreleased Deneb parts?

Because in this very forum someone posted a photo several months ago suggesting he works for AMD. I don't know if that's true and he won't tell you anything probably, so let's wait till his response.

[ryboto]

Because in this very forum someone posted a photo several months ago suggesting he works for AMD. I don't know if that's true and he won't tell you anything probably, so let's wait till his response.

So what if he works for AMD...my dad works for IBM but he doesn't know what kind of pricing scheme unreleased products are going to have.

[STaRGaZeR]

So what if he works for AMD...my dad works for IBM but he doesn't know what kind of pricing scheme unreleased products are going to have.

Erm... does your dad work in the section of IBM that is in charge of pricing the CPUs? :/

[ryboto]

Erm... does your dad work in the section of IBM that is in charge of pricing the CPUs? :/

Erm...Does the guy in this thread?

[duploxxx]

So amd launches 3ghz plus and no sub 3ghz chips?

All we know for now deneb is at most on par with kentsfield, which still leaves yorkfield 5-10% faster then kentsfield/deneb.

With the Q9400 already screatching the 200€ mark, i still dont see how amd can ask more then 200€ for a proc, even when deneb is released with 3ghz stock. Plus it still is some time till we see deneb which will leave intel time to adjust prices accordingly.

I can draw this conclusin since most of the the time a 2,66ghz Q9450 is on par with the "old" QX6850. (http://techreport.com/articles.x/14573/1) Sometimes the QX6850 wins, sometimes the Q9450.

For myself i would like to see that amd has a processor that more worth then 200€, but for what i know today that ain't gonna happen.

amd launches 2,6-2,8-3,0GHZ in first am2+ batch

again show the links where you draw your conclusion that it matches kents... and not York.

and perhaps check some benches done already where phenom is not that far behind york in performance...

http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=3344&p=14
http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=3344&p=15

[Shintai]

amd launches 2,6-2,8-3,0GHZ in first am2+ batch

again show the links where you draw your conclusion that it matches kents... and not York.

and perhaps check some benches done already where phenom is not that far behind york in performance...

http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=3344&p=14
http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=3344&p=15

According to your links, plus what we know of 65->45nm Phenom...It might just match kentsfiend in average.

You would have to cherry pick out of the average to show otherwise.

[duploxxx]

According to your links, plus what we know of 65->45nm Phenom...It might just match kentsfiend in average.

You would have to cherry pick out of the average to show otherwise.

lol check those links again and maybe for once get rid of the pink glasses you use when you look at intel benches..... kent and york aren't that far away from each-other performance wise neither is the phenom all within 5-10% ranges.

btw you know nothing about deneb performance and release. just read about 1 es sample that was on low spec.

keep on reading and dreaming that's where you always end up.

[Eternalightwith]

Wow, I think this is the closest you've gotten to AMD = Kentsfield. ;)
We'll make a convert out of you yet!


David

P.S. I'm just teasing you a little :D


According to your links, plus what we know of 65->45nm Phenom...It might just match kentsfiend in average.

You would have to cherry pick out of the average to show otherwise.

[keithlm]

All we know for now deneb is at most on par with kentsfield, which still leaves yorkfield 5-10% faster then kentsfield/deneb.


Who is the "we" you speak of? Do you have a mouse in your pocket?

In the real world "we" don't currently have enough information to make any determinations.

[Hornet331]

amd launches 2,6-2,8-3,0GHZ in first am2+ batch

again show the links where you draw your conclusion that it matches kents... and not York.

and perhaps check some benches done already where phenom is not that far behind york in performance...

http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=3344&p=14
http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=3344&p=15

we have that done already, phenom is slower clock for clock then kentsfield, or maybe you suggest its ok to compare a 2,4ghz model to a 2,6ghz one. :p:

for you to read (http://www.xtremesystems.org/forums/showthread.php?t=197466), contains quite some nice information regarding deneb, also uses the techreport agena review to show how much slower agena is compared to kentsfield.

[STaRGaZeR]

Erm...Does the guy in this thread?

I don't know, that's why I'm ASKING. Your point? :rolleyes:

[ryboto]

I don't know, that's why I'm ASKING. Your point? :rolleyes:

The way I interpretted your post was that you expected him to know, you weren't asking him if he was in the marketing dept...either way, I think we can all assume these will be sub $300 parts if the clock speeds are above 2.6ghz.