AMD propus in Q1/09

[justapost]

Propus processors without cache in the third level will also pass to the 45 nm technology . It is known that their frequency range will lie within the limits 2.3-2.6 GHz, TDP level will not exceed 65 W. Propus will present the first four core AMD processor with TDP level not more than 45 W.
Source: http://xtreview.com/addcomment-id-5592-view-AMD-Propus-in-Q1-2009.html

45W-65W is an impressive TDP. I'm really curious how those will clock without the L3 cache. :yepp:

[SocketMan]

Source: http://xtreview.com/addcomment-id-5592-view-AMD-Propus-in-Q1-2009.html

45W-65W is an impressive TDP. I'm really curious how those will clock without the L3 cache. :yepp:

Sounds like a mobile part no ?
Good find regardless:up:

[justapost]

Sounds like a mobile part no ?
Good find regardless:up:
It's not a mobile part, look at this one year old roadmap.
http://pics.computerbase.de/2/0/6/2/2/2.png
I wonder what the dual and triple cores will consume 2009. I mena, they skipped Kuma and Agena FX on 65nm but not 45nm versions.

[Rammsteiner]

Wait, Im confused, doesnt Agena have shared L3 cache too?

Just wondering since Deneb mentions shared L3 specifically:confused:

[justapost]

Wait, Im confused, doesnt Agena have shared L3 cache too?

Just wondering since Deneb mentions shared L3 specifically:confused:
Seems they use the term shared L3 starting with 45nm chips. I assume OMB L3 means something like without L3. :shrug:

[Rammsteiner]

Seems they use the term shared L3 starting with 45nm chips. I assume OMB L3 means something like without L3. :shrug:
Strange, I would almost think from that roadmap Agena doesnt have shared L3 cache. Talking about shared cache, doesnt Intel use shared L2 on their current CPU's?

Ive no clue of how things would fit in a CPU etc, so plese feel free to correct me on the things Im going to say now if it turns out be wrong or even crap:p:

Why doesnt AMD do the following with the 'space' gained from 65nm to 45nm?

1. Change L2 cache to 2MB shared
2.1 Increase L2 cache to 1MB/core
2.2 Change L2 cache to 4MB shared
3. Use the rest of the available space for L3 cache

Changing the current 512KB/core to 2MB shared would improve things even more in single threaded applications because the core used for that application can get close to 2MB of L2 cache for its own. Not too hard to guess, either of the above but then doubled would even be better.

But as I said, if there's huge fail in the above, please correct me:p:

And 0MB L3 means no L3 cache I think. Although it would be better if they put all available Lx cache there with their amount, that could be less confusing (so if 0MB L3 cache, just dont put it there).

[informal]

Rammsteiner,changing cache sharing policies on the fly,like from Agena->hypothetical Deneb(with large shared L2) is highly unlikely since it costs a lot of time(they would need to reorganize the whole cache structure with prefetching to make use of the larger shared L2).
Now with the "real" Deneb we know will show up,it would be easier to make the L3 mostly inclusive(but i doubt they changed it in that way,it probably stayed the same as in K10 65nm) and make it 3x larger.If they somehow managed to decrease latency of the 3rd level of cache and increase the speed to that of the cores,it might bring some noticeable improvements ,especially in threaded applications.
The large shared L2 would be beneficial to client/desktop applications while it would be probably detrimental in the server space.

[Macadamia]

informal, would Propus be faster in mainly single threaded heavy INT/FP applications? And how big of an impact do you expect on multicore scaling (> or < Yorkfield in scaling &#37;)?

65W is a nice sigh- OCs should be back, hopefully with a nice revenge :D

[AlabamaCajun]

Puma is the mobile and it is being launched on 65nm. Kuma was canned. Deneb will have 6M L3, Propus is neutered or L3.
Why more L3 and not L2. Seems Intel also sees it as an advantage. When it's economical to add more cache per core, we may see them again but from what I've seen on Desktops, they ether run 1 single thread app or a bunch of smaller threads and on occasion 2 apps. Considering that scenario, a single game app can have access to a large L3 pool where 4 smaller threads can share it. It works out to the optimal working on die RAM that will work across a spread of apps. I think the FX should have 1M per core, DAAMMIT, we pay more for them.

[Gen3SiS]

Newbie here and ask some questions, what is Shared L3 and does it making processor fast? 45nm deneb consume less power then agena n high frequency then agena?

[BrowncoatGR]

It's probaby just a slip by whoever did the slides. I wouldn't read too much into it

[informal]

informal, would Propus be faster in mainly single threaded heavy INT/FP applications? And how big of an impact do you expect on multicore scaling (> or < Yorkfield in scaling %)?

65W is a nice sigh- OCs should be back, hopefully with a nice revenge :D

If i would have to guess,i'd say Propus will be 10% or less faster than Agena@the same clock in single threaded apps.In multithreaded cases,who knows,it will be probably equal or slower,i really can't tell what the absence of slowish L3(at least in Agena's case) would do to the performance in that scenario.
What i really hope in the whole Shaghai refresh is :1) lower latency for some int instructions and more fastpath ones;2) lower TDP for at least one speed grade if not more(ie. what was 2.6Ghz 140W now will be 2.6Ghz <=95W;we already know there will be 95W 2.8ghz Deneb chip according to digitimes/HKEPC) ; 3)faster L3 cache with lower latency and 4)inclusion of SSSE3 and SSE4.1 instruction sets.

Now,1) is possible and 2) is a given since AMD moves to 45nm(from physics perspective,lower power cons.,less leakage + maybe even lower due to low-k- if they use low-k in 1st iteration of chips).
3) is very possible since they certainly must have worked at L3 optimizations in some way .
4) is a possibility that i personally hope will happen and would really like to see materialize since it should give the same advantages to AMD chips when SSE4.1 instructions come into play.Don't forget we've seen the PDF (http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25481.pdf) that indicates the possibility of SSSE3,SSE4.1 in 45nm chips.

All the above could mean -what AMD states - as the average 15-20% perf. increase per clock Shanghai should bring(over first K10 cores).This also means that K10 in its first form(65nm) wasn't quite "polished" and that they left some of the things in design to be implemented at 45nm process,where they would have a TDP headroom to do so(K10 65nm is a very large chip and they had to make certain trade-offs when it comes to design).
All this probably won't be enough to match Nehalem but will make them still quite competitive in server and very competitive in desktop segment(where single threaded apps dominate ,at least for now).

[jcool]

Propos? Lol? What kind of crap name is that :D
Sorry, I think it's hilarious :ROTF:
Let's just hope that performance-wise, it's not as much a joke as its codename...

[demonkevy666]

If i would have to guess,i'd say Propus will be 10% or less faster than Agena@the same clock in single threaded apps.In multithreaded cases,who knows,it will be probably equal or slower,i really can't tell what the absence of slowish L3(at least in Agena's case) would do to the performance in that scenario.
What i really hope in the whole Shaghai refresh is :1) lower latency for some int instructions and more fastpath ones;2) lower TDP for at least one speed grade if not more(ie. what was 2.6Ghz 140W now will be 2.6Ghz <=95W;we already know there will be 95W 2.8ghz Deneb chip according to digitimes/HKEPC) ; 3)faster L3 cache with lower latency and 4)inclusion of SSSE3 and SSE4.1 instruction sets.

Now,1) is possible and 2) is a given since AMD moves to 45nm(from physics perspective,lower power cons.,less leakage + maybe even lower due to low-k- if they use low-k in 1st iteration of chips).
3) is very possible since they certainly must have worked at L3 optimizations in some way .
4) is a possibility that i personally hope will happen and would really like to see materialize since it should give the same advantages to AMD chips when SSE4.1 instructions come into play.Don't forget we've seen the PDF (http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25481.pdf) that indicates the possibility of SSSE3,SSE4.1 in 45nm chips.

All the above could mean -what AMD states - as the average 15-20% perf. increase per clock Shanghai should bring(over first K10 cores).This also means that K10 in its first form(65nm) wasn't quite "polished" and that they left some of the things in design to be implemented at 45nm process,where they would have a TDP headroom to do so(K10 65nm is a very large chip and they had to make certain trade-offs when it comes to design).
All this probably won't be enough to match Nehalem but will make them still quite competitive in server and very competitive in desktop segment(where single threaded apps dominate ,at least for now).

I think AMD's cores are too tightly packed togther tbh.

the intel cores surface area seem be huge especially for nelahem.

[informal]

Propos? Lol? What kind of crap name is that :D
Sorry, I think it's hilarious :ROTF:
Let's just hope that performance-wise, it's not as much a joke as its codename...

Ok,i'll try to be not too harsh in this response.
First of all,read carefully next time,it's called PROPUS.Not PROPOS!
Second,Propus is just a code name for the core and it's after a star called Propus,which in turn is in line with AMD's Stars line of cores(Stars represent a K10 based Phenoms).45nm Desktop chip will be also called Phenom,no matter on which technology(65nm or 45nm) it's based.
Remember Yorkfield and Kentsfield?Both are codenames ,and at the end both are sold under Core2Quad brand name.Same will go for Propus and Agena(btw,Agena is the codename for 65nm Phenom chip... oh Agena is a star,no surprise huh?).

Next time,less laughter,more reading and more contributing to the topic at hand :).

[perkam]

It's not a mobile part, look at this one year old roadmap.
http://pics.computerbase.de/2/0/6/2/2/2.png
I wonder what the dual and triple cores will consume 2009. I mena, they skipped Kuma and Agena FX on 65nm but not 45nm versions.DDR3 has been delayed to 2010 last I heard.

Perkam

[jcool]

Ok,i'll try to be not too harsh in this response.
First of all,read carefully next time,it's called PROPUS.Not PROPOS!
Second,Propus is just a code name for the core and it's after a star called Propus,which in turn is in line with AMD's Stars line of cores(Stars represent a K10 based Phenoms).45nm Desktop chip will be also called Phenom,no matter on which technology(65nm or 45nm) it's based.
Remember Yorkfield and Kentsfield?Both are codenames ,and at the end both are sold under Core2Quad brand name.Same will go for Propus and Agena(btw,Agena is the codename for 65nm Phenom chip... oh Agena is a star,no surprise huh?).

Next time,less laughter,more reading and more contributing to the topic at hand :).

Ok ok, sorry. I still think it's funny though xD
Oh and I do now what codenames are, by the way ;)
OT: If they can get the TDP down and clockrates up, it might be any good. Still has to make up for the missing L3 though... Not really revolutionary tech in any case. :(

[justapost]

DDR3 has been delayed to 2010 last I heard.

Perkam
Wasn't that on the server side?
The roadmap i posted was just to show propus us a desktop part. :).
It was posted on a few news sites in march this year, so it's outdated.

[Rammsteiner]

Ok ok, sorry. I still think it's funny though xD
Oh and I do now what codenames are, by the way ;)
OT: If they can get the TDP down and clockrates up, it might be any good. Still has to make up for the missing L3 though... Not really revolutionary tech in any case. :(
Depends, if the NB can be clocked a lot higher now due to L3 removal and CPU in general as well, Im not so sure if it would perform bad because of it.

Although I think it wont outperform L3 cache Phenoms though. AMD barely hits around 4Ghz, so whatever eventual OC bump it might get from it, with current Phenoms already slowly hitting 3Ghz+ I dont think Propus will be able to clock to the level where it would outperform them.

But it's still a nice budget chip though:yepp:

[SocketMan]

Propos? Lol? What kind of crap name is that :D
Sorry, I think it's hilarious :ROTF:
Let's just hope that performance-wise, it's not as much a joke as its codename...

I am glad it made you laugh, that must have been the reason for this thread
perhaps AMD should use "caine" for it's CPU's ?

Introducing all new octocaine! Inspired by a drug addicted octopus !

- pure propane and no cocaine, yet it has an extra gain - without any pain



Now back to the topic in hand: the chart is obsolete,for all we know there won't be a "Propus". As for taking out L3, that's fine with me AMD can stick
a gpu in it instead.

EDIT**
just picked up an imc from the future;)

[BrowncoatGR]

EDIT**
just picked up an imc from the future;)

If you read the bios programmer guide you'll see that K10s IMC already supports DDR3

[justapost]

Without an L3 cache that chip will not have a tweakable onchip nb. So it should overclock in the same way k8'2 did no need for nb vid's fid's and did's. :rolleyes:
I wonder if this chip will reduce the cpu vid in CnQ on an old AM2 board like the k8's did. The k10 chips can not use a lower vid because the nb still requires a high one and those are dependant on old AM2 boards.

[SocketMan]

If you read the bios programmer guide you'll see that K10s IMC already supports DDR3


I was responding to Perkam's post about ddr3 getting supported only in 2010,my sense of humor is volt modded and overclocked to xtreme;)
in fact id you search the BKOG for "ddr3" it will come up at least 20 times,so yes it is already supported just need someone to make a mobo with it.
Chances of that however are non existent.

[Macadamia]

Thanks for the lengthy reply, informal.

All we can hope is that AMD does a "RV770" on Propus/Deneb. ;)

At this stage I think it's more like a RV670 (just back in the game, still slower; but much less slower and actually likeable for the masses), and the next step after this will be the big one :p


@Justapost

What about Griffin? No L3 I think, and multi P-states... ;)

[justapost]

@Justapost
What about Griffin? No L3 I think, and multi P-states... ;)
:yepp: That will be an interesting chip. It uses an third p-state with 1/4 frequency and allows independant vid's for the two cores in oposite to current k10 whom use the highest used p-state's vid for all cores.

[Mechromancer]

Depends, if the NB can be clocked a lot higher now due to L3 removal and CPU in general as well, Im not so sure if it would perform bad because of it.

Although I think it wont outperform L3 cache Phenoms though. AMD barely hits around 4Ghz, so whatever eventual OC bump it might get from it, with current Phenoms already slowly hitting 3Ghz+ I dont think Propus will be able to clock to the level where it would outperform them.

But it's still a nice budget chip though:yepp:

Can the L3 cache be turned off in the BIOS on AM2+ motherboards? If so we could actually test how a Phenom performs sans L3 cache. We could also test if the Northbridge can be clocked much higher.

I personally believe this whole NB problem will be remedied in the 790GX chipsets with the SB750. The 790GX is a 55nm part and northbridge stability will be taken out of the equation completely on high end boards. Actually I think the 780G is capable of going pretty high. The only bottleneck there is the actually L3 on the K10 at that point.

[Rammsteiner]

Nah, cant disable L3 AFAIK.

[demonkevy666]

Can the L3 cache be turned off in the BIOS on AM2+ motherboards? If so we could actually test how a Phenom performs sans L3 cache. We could also test if the Northbridge can be clocked much higher.

I personally believe this whole NB problem will be remedied in the 790GX chipsets with the SB750. The 790GX is a 55nm part and northbridge stability will be taken out of the equation completely on high end boards. Actually I think the 780G is capable of going pretty high. The only bottleneck there is the actually L3 on the K10 at that point.

L3 a bottleneck bull:banana::banana::banana::banana:.

it's faster then system memory.

the 780G has a separate South bridge clock. the jetway HA06 can rise & lower it.

I don't think the 700SB has those problems. I think it just couldn't handle the SATA 3.0 clocks.

disabling the L3 cache wouldn't help at all. it would make a single threaded performance drop.

I'm better those new 45nm Phenom can clock L3 cache to clock speeds or higher thats what it really needs.

[Rammsteiner]

L3 is a bottleneck in the sense of pre-L2 buffer I think:confused:. I mean, in the end everything is a bottleneck. Lets say your CPU is a bottleneck for GPU's, you upgrade/OC CPU, then basicly GPU's are a bottleneck for the CPU since the CPU cant run 100%;). Stupid thinking, but true. That's how you might look at L3 being a bottleneck on a more serious view.

SB700 not being used much apart from value-ish boards... I think it's because they knew SB750 was going to come. If we all went monkey about SB700 turning out still not offering SB750 performance, then we had to buy a new board again and people would complain I think.

TBH, Im happy they didnt do much with SB700, because I would have updated. And then now again, I would have updated again but not happily though.

At some point you accept SB600 is crap, set everything stock and wait. Although, I did:D In the end stock 9850 can do its job. Altough you notice a performance degrade from 3.5Ghz 6400+ to 2.5Ghz Phenom but well, I guess it's worth it:yepp:

[K20]

Why doesnt AMD do the following with the 'space' gained from 65nm to 45nm?

1. Change L2 cache to 2MB shared
2.1 Increase L2 cache to 1MB/core
2.2 Change L2 cache to 4MB shared
3. Use the rest of the available space for L3 cache

AMD claimed that most applications use 512KB of L2, Nehalem will have 256KB of L2.
AMD has been using 1MB (this was quickly phased out of atleast the consumer space)/512KB/256KB (value line) per core of L2 cache for years while Intel has been using extremely large cache sizes of 4MB shared between two cores and now 6MB shared between two cores.

Maybe the applications where Phenom isn't doing so well were designed with the assumption that they would be in a system with a large amount of L2 cache?

http://www.digit-life.com/articles2/cpu/rmmt-l2-cache.html - link showing the inefficiency of Intel's shared L2 when both cores want to use it.


L3 is a bottleneck in the sense of pre-L2 buffer I think:confused:. I mean, in the end everything is a bottleneck. Lets say your CPU is a bottleneck for GPU's, you upgrade/OC CPU, then basicly GPU's are a bottleneck for the CPU since the CPU cant run 100&#37;;). Stupid thinking, but true. That's how you might look at L3 being a bottleneck on a more serious view.

Data travels from the on die northbridge to a core's L1, old data gets booted from the L1 to the L2 and then old data from the L2 gets booted back to the northbridge (which contains the L3). Obviously that doesn't describe all the intricate data paths but the L3 is in no way a bottleneck, processor design is all about balancing bottlenecks.

The only way the L3 might get the data before the cores would be if 2 or more cores requested the same piece of data at (near enough) the same time. Once the data is in the northbridge it could transition to the owned (http://www.xtremesystems.org/forums/showpost.php?p=2990797&postcount=44) state and the cores could receive it in the shared state.

[Brother Esau]

At some point you accept SB600 is crap, set everything stock and wait. Although, I did:D In the end stock 9850 can do its job. Altough you notice a performance degrade from 3.5Ghz 6400+ to 2.5Ghz Phenom but well, I guess it's worth it:yepp:

The SB600 is Crap and as I have said all along you need a dedicated Raid Controller to see the true performance of this board:) Why all of you people will dump thousands of dollars on hardware but cannot justify true worth and Merit in a investment in a Dedicated Raid controller is beyond me:confused: The HDD is after all the Bottle neck of the entire PC not to mention that a investment in a dedicated enterprise level raid controller has to be the single best hardware investment you could possibly make hardware wise and just think you never lose you're storage data when changing Motherbords .............Foolish Mortals!:D

[biohead]

The SB600 is Crap and as I have said all along you need a dedicated Raid Controller to see the true performance of this board:) Why all of you people will dump thousands of dollars on hardware but cannot justify true worth and Merit in a investment in a Dedicated Raid controller is beyond me:confused: The HDD is after all the Bottle neck of the entire PC not to mention that a investment in a dedicated enterprise level raid controller has to be the single best hardware investment you could possibly make hardware wise and just think you never lose you're storage data when changing Motherbords .............Foolish Mortals!:D

yup and for simple RAID 0 u don't even need enterprise level cards... there are decent 4 port software cards out there for less than a hundred bucks.

[Rammsteiner]

K20, thx for explaining then. As I said, I dont know how CPU's are built up etc, so I was just guessing around;)


The SB600 is Crap and as I have said all along you need a dedicated Raid Controller to see the true performance of this board:) Why all of you people will dump thousands of dollars on hardware but cannot justify true worth and Merit in a investment in a Dedicated Raid controller is beyond me:confused: The HDD is after all the Bottle neck of the entire PC not to mention that a investment in a dedicated enterprise level raid controller has to be the single best hardware investment you could possibly make hardware wise and just think you never lose you're storage data when changing Motherbords .............Foolish Mortals!:D
If that was directed at me... Might I point you on my sig, especially the 'Storage' part, which has been there for months now? Im about SB600, not just the storage part, Im about the entire SB600 and I cant wait to kick it out of the window ASAP when SB750 arrives:shakes:.

Spider is an awesome platform, but not with a SB600.

[Brother Esau]

K20, thx for explaining then. As I said, I dont know how CPU's are built up etc, so I was just guessing around;)


If that was directed at me... Might I point you on my sig, especially the 'Storage' part, which has been there for months now? Im about SB600, not just the storage part, Im about the entire SB600 and I cant wait to kick it out of the window ASAP when SB750 arrives:shakes:.

Spider is an awesome platform, but not with a SB600.



OOOOOOOOOPS:D Good show old boy!:clap:

[Rammsteiner]

OOOOOOOOOPS:D Good show old boy!:clap::p:

Only cost me 170 Euro's, performs pretty good. Only has 2 ports though but well, I dont even manage to get one HDD full, let alone more than 2:D

[K20]

Spend lots of money on hardware raid...

I think Rammsteiner was complaining about the overclocking capabilities of the SB600. The SB750 will be connected to the directly to the CPU to somehow help stability.


K20, thx for explaining then. As I said, I dont know how CPU's are built up etc, so I was just guessing around;)

You're (http://aceshardware.freeforums.org/finally-an-image-of-shanghai-t405-15.html) welcome (http://www.chip-architect.com/news/2007_02_19_Various_Images.html):). Brisbane prefetches to it's L2 while Core prefetches (aggressively) to both it's L1 and L2.