AMD demos 45nm at Cebit.

[freeloader]

http://ca.news.finance.yahoo.com/s/04032008/34/biz-finance-news-amd-demos-45nm-native-quad-core-processors-server.html

http://www.amd.com/us-en/0,,3715_15503,00.html?redir=45nm01

No mention of speeds, but suffice it to say they have operational 45nm CPUs.

[Marvin_The_Martian]

I clicked the amd link and wanted to read the q&a on 45nm but got a 404, same for the press release link.

[freeloader]

I clicked the amd link and wanted to read the q&a on 45nm but got a 404, same for the press release link.

The links works perfect for me.

Edit: I take that back. Not working for the Q&A. :(

[fellix_bg]

I clicked the amd link and wanted to read the q&a on 45nm but got a 404, same for the press release link.
404 -- processor not found! :ROTF:

http://www.tgdaily.com/images/stories/article_images/amd/amd_45nm_425.jpg

[Nedjo]

So these are first pictures of Shanghai:

http://www.amd.com/us-en/assets/content_type/Additional/44695A_Die_single_047207_lowRes.jpg


That big yellow surface would be 6MB L3...

Comparison with Barcelona:

http://www.overclock3d.net/gfx/articles/2007/07/27192237513l.jpg

[freeloader]

So these are first pictures of Shanghai:

http://www.amd.com/us-en/assets/content_type/Additional/44695A_Die_single_047207_lowRes.jpg

http://www.amd.com/us-en/assets/content_type/Additional/44697A_Dies_1_large_lowRes.jpg

Is it just me, or do these chips look like they have more cache than the Phenoms? I'd love to see the L3 operating at full chip speed as well.

[Marvin_The_Martian]

The links works perfect for me.

Edit: I take that back. Not working for the Q&A. :(

It's up now, they must be reading XS ;)

Pics look nice, q&a dissapointing though as no performance indications can be found. Or did I look in the wrong place?

[XS Janus]

So other than a process shrink positive stuff, what new features can we expect from it?

[fellix_bg]

The L3 array is in the NB clock domain, so I don't expect to be in sync with the cores in this 45nm spin off. And above this, K10 has to maintain a specific (async) clock rate for the NB so to avoid weird DDR2 speeds, as it was the case in K8 architecture.

[freeloader]

The L3 array is in the NB clock domain, so I don't expect to be in sync with the cores in this 45nm spin off. And above this, K10 has to maintain a specific (async) clock rate for the NB so to avoid weird DDR2 speeds, as it was the case in K8 architecture.

Damn. I'd take the weird DDR2 clock speeds just to have the L3 run at full core speed. I believe the trade off would be worth it.

[Blauhung]

• Ultra-low-k Dielectrics. In some later 45nm products, AMD plans on using ultralow-k dielectrics to reduce wire delays by as much as 15 percent and enable greater overall processor performance.

• High-k/metal Gates. As part of AMD’s Continuous Transistor Improvement (CTI) approach, AMD has the option to introduce high-k/metal gates into 45nm production to further enhance transistor performance. The “gate first” approach, developed with IBM, is designed to provide a simpler, less time consuming way to migrate to high-k metal gate technology and secure benefits that include improved performance and reduced power consumption.

Doesn't look like they have everything working quite yet.

Edit, but I must say, the chips do look a little more gracefully put together then barcy, and the extra cache could be very cool.

[Syn.]

lol...

A common misconception is that being first to a new process technology generation is
the fundamental determinant of performance and energy efficiency leadership. AMD has
proven this to be false.

Rather than the more costly and higher-risk method of making a full technology
transition every two years, AMD uses a unique and highly efficient method called
Continuous Technology Improvement (CTI).

CTI allows us to maximize the benefits and increase the return on investment of a single
process technology generation for as long as possible by evolving and improving the
transistor designs within that generation. This is why at many points in our history our
processors and platforms have remained competitive, even when compared against those
from our competitors based on the next process technology generation.

AMD Q&A PDF (http://www.amd.com/us-en/assets/content_type/DownloadableAssets/AMD__45nm_Press_Q-A.pdf)

[K404]

Well..they can show it working now, it stands a chance of being on-time :)

cautiously optimistic :)

[freeloader]

lol...



AMD Q&A PDF (http://www.amd.com/us-en/assets/content_type/DownloadableAssets/AMD__45nm_Press_Q-A.pdf)

Well if you don't factor in any overclocking at all, the statement is probably true.

[Marvin_The_Martian]

Architecure > clockspeeds?

K8 vs netburst?

True, both off them but they do not have any bearing on that snip. Snip is about an excuse on how they can not keep up with intel's design teams and fabrication plants simply because their r&d is way way to low which they offcourse don't want to admit to so they want you to believe it's intentional.

[AAbenson]

...so it means end of the summer we will see some power point presentation without any real benches:mad::down: ,then late winter next year(maybe next CeBit!?) a "running" PC with the new cpu inside will be secretly demoed in a dark room under full nda ofcourse and nobody will be allowed closer than 5steps from it:down:...and maybe,maybe 2 years from now if the stars are aligned in the right configuration we will be able to buy some "early" released cpus which will hopefully work as advertised...
great stuff,im really excited,promise i wont be buying any Intel Quads runnin 4GHZ at 1.35v in the meantime.All Hail AMD:rofl:

[Marvin_The_Martian]

...so it means end of the summer we will see some power point presentation without any real benches:mad::down: ,then late winter next year(maybe next CeBit!?) a "running" PC with the new cpu inside will be secretly demoed in a dark room under full nda ofcourse and nobody will be allowed closer than 5steps from it:down:...and maybe,maybe 2 years from now if the stars are aligned in the right configuration we will be able to buy some "early" released cpus which will hopefully work as advertised...
great stuff,im really excited,promise i wont be buying any Intel Quads runnin 4GHZ at 1.35v in the meantime.All Hail AMD:rofl:

If you want to troll about Intel do it somewhere else not here. You're the first, I'm also bad for responding to it but keep the thread on topic please :)

[freeloader]

...so it means end of the summer we will see some power point presentation without any real benches:mad::down: ,then late winter next year(maybe next CeBit!?) a "running" PC with the new cpu inside will be secretly demoed in a dark room under full nda ofcourse and nobody will be allowed closer than 5steps from it:down:...and maybe,maybe 2 years from now if the stars are aligned in the right configuration we will be able to buy some "early" released cpus which will hopefully work as advertised...
great stuff,im really excited,promise i wont be buying any Intel Quads runnin 4GHZ at 1.35v in the meantime.All Hail AMD:rofl:


Don't turn this into a bashing thread. Everyone here and their grandmother knows about AMD's previous problems. Let's hope they can go forward with good success so we can all benefit from better prices and performance.

[STaRGaZeR]

lol...



AMD Q&A PDF (http://www.amd.com/us-en/assets/content_type/DownloadableAssets/AMD__45nm_Press_Q-A.pdf)

LOL :ROTF:

[Power5]

Awesome wallpaper
http://www.amd.com/us-en/assets/content_type/Additional/44701A_Wafer_2.jpg

[Periander6]

Where is the demo? All I see here is a press release and some die photos.

[vitaminc]

They also demo'ed a 3GHz Barcelona system in their Tech Analyst Day last June.

[mike8913]

this one better clock well.......:(

[Ub3r-L33ch]

AMD is still around?

[fellix_bg]

A dual-core flavour with 3MB of L3 would be a decent part. ;)

[freeloader]

A dual-core flavour with 3MB of L3 would be a decent part. ;)

How about the full 6mb L3 on a dual core. I'm greedy. :D

[informal]

How about the full 6mb L3 on a dual core. I'm greedy. :D


Better yet,how about a Montreal flavor of Shanghai with 1MB of L2 per core with 6 MB of L3 in H1 2009 :D?

[Ub3r-L33ch]

How about one that is actually as fast or faster than it's equivalent Intel processor?

[w0mbat]

AMD 45nm Deneb C0-stepping K10.5 live @ cebit
this baby was running on a AMD 780G while encoding a hd-video
http://www.abload.de/img/amd_deneb_2pb9.jpg
http://www.abload.de/img/amd_denebtef.jpg

[STaRGaZeR]

How about one that is actually as fast or faster than it's equivalent Intel processor?

Haha good one. Not gonna happen this generation.

PD: Stop posting damn bananas :p:

[Marvin_The_Martian]

Wombat it would make those pic a whole lot more usefull if they included a result :)

[spicypixel]

http://www.abload.de/img/amd_deneb_2pb9.jpg
1.6+volts?!?
Either its misreported or I just cried a little.

[w0mbat]

@Marvin_The_Martian: The result was that it didnt crash and properly finished the task :D

@spicypixel: CPU-Z cant read the vcore yet.

[spicypixel]

Ok mind at rest a bit now. I'd probably pay an arm and a leg for a dual Phenom FX 45nm PC right now.

[Helmore]

How about one that is actually as fast or faster than it's equivalent Intel processor?

That's would be like trying to go faster than the speed of light for AMD :p:

[Carfax]

I wonder how fast this will be compared to Barcelona?

No more than 10% I'd wager.

[Marvin_The_Martian]

Wombat do you know the speed the system was running at ( core's and nb? ).

[whocaresbg]

I wonder how fast this will be compared to Barcelona?

No more than 10% I'd wager.

Up to 30% according to Fudzilla and other chinese sources :cool: .

[Nedjo]

The L3 array is in the NB clock domain, so I don't expect to be in sync with the cores in this 45nm spin off. And above this, K10 has to maintain a specific (async) clock rate for the NB so to avoid weird DDR2 speeds, as it was the case in K8 architecture.

DDR2 clocks speed isn't reason for async speed of L3 in comparison to the cores.

As you aware K10 can independently clock all four cores, but since they must continue to communicate despite different clocks, clock of L3 must stay unchanged…

It would be excellent if L3 would run in sync with cores, but 'cos of thermal budget you must make tradeoff there, and it's proven that gain from core clocking is always bigger then from L3 clocking.

[Extelleron]

I wonder how fast this will be compared to Barcelona?

No more than 10% I'd wager.

From what has been reported, 10-20% on average.

Barcelona -> Shanghai is a bigger move than Conroe -> Penryn. Shanghai has 3X the L3 cache in addition to some core improvements.

Hopefully Shanghai will do what Barcelona was supposed to and run the NB/L3at a HIGHER frequency than the CPU. That alone could improve performance by up to 5-10%.
So in theory Shanghai should be slightly faster than Penryn clock-for-clock but it will get demolished by Nehalem.

[fellix_bg]

DDR2 clocks speed isn't reason for async speed of L3 in comparison to the cores.
Well, let's say it's one of the reasons, or more exactly -- a very intentional subsequent effect. ;)

[ubuntu83]

So in theory Shanghai should be slightly faster than Penryn clock-for-clock but it will get demolished by Nehalem.

but Nehalem will need a newer socket because of it's larger size.

[informal]

So in theory Shanghai should be slightly faster than Penryn clock-for-clock but it will get demolished by Nehalem.

I highly doubt that CSI in Nehalem will bring anything to the table -compared to Penryn- when desktop is in question.I think that Penryn's high freq. FSB will NOT be slower than CSI I/O we will see in Nehalem,at least in desktops.Also HyperThreading could potentially speed it up a bit in multithreading apps,but still needs to be seen by how much.

[Nedjo]

So in theory Shanghai should be slightly faster than Penryn clock-for-clock but it will get demolished by Nehalem.

Here we go again with flame war in sight…
:down:
Can't we avoid it this time and concentrate to the fact that AMD promised rampup of 45nm production in H1, and delivered! We're promised 45nm CPU's for sales in H2, and looks like AMD will deliver… in contrast to all those Intel fanboys who did screaming around that it's highly unlikely that AMD will deliver 45nm parts in 2009! :rolleyes:

[Nedjo]

I highly doubt that CSI in Nehalem will bring anything to the table -compared to Penryn- when desktop is in question.I think that Penryn's high freq. FSB will NOT be slower than CSI I/O we will see in Nehalem,at least in desktops.Also HyperThreading could potentially speed it up a bit in multithreading apps,but still needs to be seen by how much.
informal please don't... if you understand me...

[fellix_bg]

CSI (as HTT) is primary intended to improve multi-socket scaling over the stagnant FSB-based topology.

[Extelleron]

Here we go again with flame war in sight…
:down:
Can't we avoid it this time and concentrate to the fact that AMD promised rampup of 45nm production in H1, and delivered! We're promised 45nm CPU's for sales in H2, and looks like AMD will deliver… in contrast to all those Intel fanboys who did screaming around that it's highly unlikely that AMD will deliver 45nm parts in 2009! :rolleyes:

I think you're getting the wrong idea from my post. I'm not an Intel fanboy and I currently own an AM2 X2 system. I'm glad AMD is on track with 45nm and I hope we will really be able to buy one of these at newegg within the Q3timeframe.

I don't think anyone seriously thought AMD wouldn't deliver 45nm in 2009; they doubted the delivery of 45nm in Q3 2008. You can't really blame them as AMD didn't really execute well in 2007 with the exception of RV670 actually being released earlier than expected.

As Fudzilla stated a few days ago... Shanghai will be smaller and cheaper than Nehalem, but it will be slower and that is a given at this point. If AMD is able to hit the right frequencies and position tri-core at a good price and undercut the quad-core Nehalems with quad-core Shanghai, then I think they will be sucessful.

Of course this depends on how much faster Nehalem is clock-for-clock, but I would assume it will demolish Penryn & Shanghai in multi-threaded apps because of SMT and the ability to execute 8 threads on a Quad-core CPU. And I think we should expect Nehalem to be much faster... AMD is still bringing a (now) 5-year old architecture to the table to compete against two NEW architectures from Intel.

[metro.cl]

AMD 45nm Deneb C0-stepping K10.5 live @ cebit
this baby was running on a AMD 780G while encoding a hd-video
http://www.abload.de/img/amd_deneb_2pb9.jpg
http://www.abload.de/img/amd_denebtef.jpg

Any idea of clock speeds?

[Marvin_The_Martian]

More intel discussion in this Amd thread?

Idk who's not getting it Extelleron, but a bird just told me the name starts with an E.

I'm glad AMD is delivering, just as you are Nedjo. Now they need to send me a few test samples offcourse :d

And I really want to know both the speed they demo'd at and the initial launch speeds for the 45nm process.

Edit: Metro get in line I asked first :up: (#37)

[[XC] gomeler]

This is exciting. Deep down a small part of me wants to play with a Phenom and K10.5 might give me the option to do it without the performance part of me disowning the rest of me.


...so it means end of the summer we will see some power point presentation without any real benches:mad::down:... blah blah blah

It is a very good thing my name isn't in a darker color or you'd have a temporary vacation. Rawr :cool:

[informal]

Let's just stop the Nehalem talk and concentrate on 45nm K10.
From the Cebit today came the information that Shanghai will consume 15% less power than 65nm Barcelona parts.So this is very good news.Also this is not a straight shrink of the core since the 3x larger L3 cache and some core changes.This thing will definitely be better per clock and per./watt(even more so) than Barcelona\Phenom.AMD just needs to hard launch this baby in Q3/Q4.

[Marvin_The_Martian]

Let's just stop the Nehalem talk and concentrate on 45nm K10.
From the Cebit today came the information that Shanghai will consume 15% less power than 65nm Barcelona parts.So this is very good news.Also this is not a straight shrink of the core since the 3x larger L3 cache and some core changes.This thing will definitely be better per clock and per./watt(even more so) than Barcelona\Phenom.AMD just needs to hard launch this baby in Q3/Q4.

Hard launch and 3g+ launch (stock) speeds please... pretty please :cool:

[Mav451]

I wouldn't mind a high-clocking tri-core. It's basically a dual-core with an extra core for alt-tabbing out of a dual-threaded optimized game. I'm looking for an e8400 equivalent from these new AMD 45nms...if they can pull something like that off (same price range), I'll return to the home land haha.

[Marvin_The_Martian]

This thread isn't about tri cores but native quads ;)

[w0mbat]

clk should be <2GHz w/ this model

[SparkyJJO]

Wondering if it would be a worthwhile upgrade from my current 9600BE I just got... depends on price, performance, and how much of an OC I can get out of my current chip (way too busy to OC right now - 36 hours work + 13 hours school + homework + eating + sleeping = no time to OC :()

[grunge100]

Things are starting to look better for AMD:clap: :clap:

Any word on the Puma platform yet?

[Marvin_The_Martian]

clk should be <2GHz w/ this model


That's just early silicon right? Anyone have some insight already at which speeds these will launch?

[FischOderAal]

That's just early silicon right? Anyone have some insight already at which speeds these will launch?

I wouldn't call C0 early silicon ;)

AMD 45nm Deneb C0-stepping K10.5 live @ cebit

can't wait to get my hands on AM3 :) haven't messed around with an AMD rig for too long.

[Marvin_The_Martian]

but <2ghz can't be a real clock speed unless this was their slowest lowest offering and that wouldn't quite fit the 'showcasing tech' standpoint right? I'm just hoping 45nm will bring Amd closer to the oc potential off them other chips from Redmond.

[Periander6]

I wouldn't call C0 early silicon ;)


Since the A and B series were Barcelona/Phenom, it's actually as early as it gets.

[informal]

The purpose of the showing was not the clocks but to show that the design works well in the present form and can run software error free today.The clocks should be higher than Agena FX that will come in late Q2(2.7/2.8GHz).So i expect them to launch a new FX chip at the 2.8GHz in Q3 or if it slips maybe in Q4,with 2.6Ghz in Q3 then.These chips will have lower TDP/power requirements than 65nm Phenoms and will probably OC much better(since they have same current limitation for the socket AM2+,both for cores and IMC and this means that they can run with lower voltages for the same clocks as Agenas)

[FischOderAal]

Since the A and B series were Barcelona/Phenom, it's actually as early as it gets.

:doh: sry

I'm afraid I'm not very familiar with AMDs procs

[BrowncoatGR]

Since the A and B series were Barcelona/Phenom, it's actually as early as it gets.

It also looks like B3 beeing the last revision of K10 might be true

[Nedjo]

Hard launch and 3g+ launch (stock) speeds please... pretty please :cool:

Well if you take in to account AMD's history of manufacturing transitions. You'll notice pattern from which one can conclude that first revision of the new manufacturing process is focused on bigger yields rather than higher frequency bins.

K8 first revision – Clawhammer – 130nm was all about getting as much as possible dies out from the factory! Getting from initial 2 GHz to 2.2 GHz was harder that today for K10 to get from 2.2 to 2.4 GHz!

K8 second revision – NewCastle – 130nm allowed reaching 2.4+ GHz, and those advances was implemented in Clawhammer (1MB L2 version) later on, so those chips also reached 2.4+ GHz…

Transition from NewCastle and 130nm to Winchester and 90nm resulted in smaller chips and bigger output from 200mm wafers, but equal clocking capability to proven and mastered 130nm tech. With arrival of 90nm Venice core, things started to change in fawor of 90nm tech!

With Windsor AMD squeezed maximum from 90nm tech, but between Winchester and Windsor there were Venice, San Diego, Manchester, Toledo, Orleans! So it's no wonder that with arrival of the first 65nm core – Brisbane it's predecessor Windsor was more overclockable! But, AMD needed just one revision of 65nm tech to surpass excellent previous tech. I'm talking about G2 Brisbane

I do believe that B3 revision of Agena will bring little speed up, and we'll finally get faster CPUs in compassion to Phenom 9600! Also I believe that Deneb's main purpose is to bring bigger K10 output thanks to smaller chips, and that speed gains in terms of clocks will not be spectacular. It's just common business sense.

But second revision of 45nm, the one that'll bring Ultra-Low-K tech will bring significant clock improvements, just as AMD stated in their FAQ about 45nm tech.

[Marvin_The_Martian]

Yeah they need those faster gates I remember now having heated arguments about this with someone stating Amd could reach the same clocks as Intel using their current process.

Think I wasn't paying to much attention to all the details atm.

But using older generations to predict the future is something which can bite you in the behind, it's not like tech developments follow historical rules.

[Piotrsama]

Best AMD news in a long time.
Looks very nice.

[zakelwe]

20% improvement is good news over 65nm K10, is this IPC or due to increased speed? If it is IPC then what is the major change that has given them this boost?

Regards

Andy

[P.I.M.P_SLi]

20% improvement is good news over 65nm K10, is this IPC or due to increased speed? If it is IPC then what is the major change that has given them this boost?

Regards

Andy

10-20% IPC improvement due to far bigger L3 cache and several tweaks to the core.

[dinos22]

this is unexpected

hopefully we'll get to see them fulfill the promise this time round even though half yearly estimates are large enough

so December this year maybe :d hehe

macci please do something about those damn cold bugs :D

[JumpingJack]

this is unexpected

hopefully we'll get to see them fulfill the promise this time round even though half yearly estimates are large enough

so December this year maybe :d hehe

macci please do something about those damn cold bugs :D


<edited> meh, that guy was clueless (reference to something completely different, and way out of left field, ignore this) -- AMD has focused on 45 nm now for sometime, my general gut instinct is they got 65 nm to an acceptable (not perfected) point then put all resources... so it may indeed turn out well.

[MotF Bane]

Evidently Shanghai and Deneb are already shipping:

http://www.informationweek.com/news/showArticle.jhtml?articleID=206901459&subSection=News

Now we just have to wait a little bit, and then samples will almost certainly show up here. :up:

[da-key]

Voltage at 1.64 is a bit interesting. How much headroom can it have already that high?

:confused:

[JumpingJack]

Now we just have to wait a little bit, and then samples will almost certainly show up here. :up:

:) Ahhh, I edit the link out... that guy obviously confused AMD's sampling of B3 65 nm with 45 nm Shanghai demo.

[informal]

Voltage at 1.64 is a bit interesting. How much headroom can it have already that high?

:confused:

Voltage reading is not correct..
Ahhh, I edit the link out... that guy obviously confused AMD's sampling of B3 65 nm with 45 nm Shanghai demo.

I think he maybe was implying that AMD shipped the ES 45nm parts to major partners for validation and testing purposes.

See here:
Advanced Micro Devices on Tuesday said samples of its first 45-nanometer processors have been shipped to computer manufacturers, and the company is on track to start production in the second half of the year.

[JumpingJack]

Voltage reading is not correct..

:) How do you know? Though it does seem excessively high, CPUID does not get the voltage from the CPU, but takes it from the DAC that sets it via the BIOS ... typically a Winbond or AD chip.

For a first silicon, it would not be out of the ordinary to have a voltage this high to get a working sample (or at least I suspect), and frankly is nothing to be concerned about... this is not final silicon.

[Jaivan]

gomeler;2815968']This is exciting. Deep down a small part of me wants to play with a Phenom and K10.5 might give me the option to do it without the performance part of me disowning the rest of me.

LOL, thats kind of how i feel after getting this phenom rig, but if 45nm is really as good as they say it is then i guess it was worth it.

[cpuz]

@spicypixel: CPU-Z cant read the vcore yet.

Yes correct, the real vcore is around 1.3V afaik.

[donitsi]

@Marvin_The_Martian: The result was that it didnt crash and properly finished the task :D

@spicypixel: CPU-Z cant read the vcore yet.

It's aliiive! IT'S ALIVEE!!! :shocked:
Starts looking good for AMD :up:
This is much better demo than 65nm k10 ehh? (taskmanager anyone?) :ROTF: :rofl:

[BadNizze]

Looks like AMD is on track for late Q4 this time.... Crossing fingers. Know we need som decent mobo´s to...

[GunterFalstaff]

sounds awesome for amd... but i cant wait for the 22nm processors! =P

http://blogs.cnet.com/8301-13924_1-9880862-64.html

[FischOderAal]

well... EUV is due to 2016 ;) so we're gonna mess around with 32 nm structures for quite a while. the only thing that will matter then will be the architecture.

[w0mbat]

16 core shanghai server rig (4x shanghai 45nm k10.5 quad-core c0-stepping) @ cebit
vcore is correct here, clk unknown
http://www.abload.de/img/shanghai_16capc.jpg
http://www.abload.de/img/shanghai_16c_20ko.jpg

[spicypixel]

Now thats a sight for sore eyes...

[informal]

:) How do you know? Though it does seem excessively high, CPUID does not get the voltage from the CPU, but takes it from the DAC that sets it via the BIOS ... typically a Winbond or AD chip.

For a first silicon, it would not be out of the ordinary to have a voltage this high to get a working sample (or at least I suspect), and frankly is nothing to be concerned about... this is not final silicon.

Read the post made by CPU-z author,below :) :
Yes correct, the real vcore is around 1.3V afaik.

Also look at the latest post made by wombat containing pictures of 16 cores machine utilizing Shanghais,now with VCore readings @1.15V.

[Morais]

wow 16 cores :slobber:

[Nedjo]

Yes correct, the real vcore is around 1.3V afaik.
dude just want to use opportunity and say congrats for amazing little util that become must for Intel and AMD in showing their new products!

[Marvin_The_Martian]

I would love a cinebench from that :up:

[cpuz]

dude just want to use opportunity and say congrats for amazing little util that become must for Intel and AMD in showing their new products!

thanks :up:

[STaRGaZeR]

Read the post made by CPU-z author,below :) :


Also look at the latest post made by wombat containing pictures of 16 cores machine utilizing Shanghais,now with VCore readings @1.15V.

Please, do not confuse vCore with Core VID ;)

[spicypixel]

All we need to know is clockspeed. 16x 1.8/2.0ghz is not going to be as good as 8x 4.0 GHz of the Skulltrail (and its associated server equivalents) due to communications latency and overhead.

Please correct me if I'm wrong.

[w0mbat]

@spicypixel: These are C0-Stepping CPUs, they wont go retail before C1/2, so the clk-speeds theyre running now has nothing to say about the real clk-speeds when launching.

[freeloader]

@spicypixel: These are C0-Stepping CPUs, they wont go retail before C1/2, so the clk-speeds theyre running now has nothing to say about the real clk-speeds when launching.

Nothing but pure speculation on my part, but I'd wager those cores are running in the range of 1.8 to 2.2 ghz.

[spicypixel]

That's fair enough. Shame its so many months away, can't even get a decent Quad Opteron system at the moment so seems my render farm is nearly a year away

[KTE]

Well well, much a go as usual wherever AMD gets mentioned since Core 2. Hopefully less abnormality this billionth time. :)

2.8/3.0G was mentioned as the speed for the higher clocked models, if and hopefully, they believe. Don't make too much about it yet until you see something, same as with Nehalem. Wild guesswork on no info or experience really only shows ones character rather than fact.

Jack: AMD were supposed to ship 45nm samples to select customers for validation and testing around mid-April AFAIK but the B3 around 20th March. Both the B3 bug free Barcelona and the C0 Shanghai/Deneb samples were up and working well in stress testing Jan. 15th and being produced in the 300mm SOI wafer Fab 38 and Fab 36. Fab 36 has some testing toolsets for 45nm CPUs since November '07 AFAIK. However, on both fronts they were ahead of schedule and so shipped the validation samples of B3 Opteron beginning March along with some 45nm Shanghai/Deneb samples. The link you posted mainly dwelt on that as in here (http://www.eetimes.com/rss/showArticle.jhtml?articleID=206901553&cid=RSSfeed_eetimes_newsRSS) and better explained over here ("http://www.computerworld.com/action/article.do?command=viewArticleBasic&articleId=9066418).

Please, do not confuse vCore with Core VID ;)If VID is 1.150, VCore is one step higher, i.e. 1.160-1.200 depending on the CPU MSR coding. It could easily be in power saving mode, that's usually the VID/VCore for it.

[spicypixel]

This is almost the best news for AMD since their AMD 64 releases.

[Zytek_Fan]

Meh, I won't hold my breath.

[Piotrsama]

16 core shanghai server rig (4x shanghai 45nm k10.5 quad-core c0-stepping) @ cebit
vcore is correct here, clk unknown

Thx for the pics :up:
Nice monitor too BTW :p:

[Nedjo]

Meh, I won't hold my breath.
by no means don't...

It's funny to se that some people just can't come to peace with the fact that AMD isn't gone of with the ways of dodo and is in fact in preparation of big come back...

[***Deimos***]

I dunno no...

Intel using high-K gates. AMD using SOI and immersion... and probably high-K gate in later revision.

But things are getting pretty small and crowded... when AMD was shiping 130nm K8, and building new fab to make 90nm, it was difficult to image 45nm, but here we are. How will they make 32nm or 25nm... shifting masks and immersion only go so far.

[Marvin_The_Martian]

Both Intel and Amd use SOI just applied diffrently afaik.

32nm will be offcourse with the high-k gate, since the second revision off 45nm will already be based on that tech. Atleast that's what I could summarize :up:

[funnyperson1]

Damn. I'd take the weird DDR2 clock speeds just to have the L3 run at full core speed. I believe the trade off would be worth it.

Then it might as well be L2 cache, the whole point of cache hierarchies is that the lower levels of cache can be slower and therefore have higher capacities without jacking up the cost.

[NotFred]

Hmm, not just that. The L2 is per core in these chips where as the L3 is shared allowing the cores to trade data. Having it at full (core) speed could have some advantages...

[BrowncoatGR]

Immersion can go to 32nm already. From what im reading 22nm might be a possibility if better photoresists will get produced. With all the recent news about AMDs EUV tests there is a lot of speculation that AMD is targeting it for 22nm. Intel has dug itself into a hole here by not adopting Immersion at 45nm as they might have to switch again at 22nm to EUV and thats going to be costly(32nm(immersion), 22nm(EUV)). I also agree with JumpingJack that AMD seems to have stopped developing 65nm for a while now. There has been zero improvements in 65nm K8s and that says a lot.

[GoThr3k]

Both Intel and Amd use SOI just applied diffrently afaik.


as for as i know, intel uses the normal bulk cmos, not SOI

[hollo]

yeah intel uses bulk

It's funny to se that some people just can't come to peace with the fact that AMD isn't gone of with the ways of dodo and is in fact in preparation of big come back...

http://www.farfromneutral.com/exodus/wp-content/uploads/2007/03/o_rly.jpg

[STaRGaZeR]

It's funny to se that some people just can't come to peace with the fact that AMD isn't gone of with the ways of dodo and is in fact in preparation of big come back...

You forgot to specify the year. My guess is 2015-2020. With lucky.

[Marvin_The_Martian]

as for as i know, intel uses the normal bulk cmos, not SOI

yeah I was getting confused about fd-soi as Intel did research into that before.

[Jacky]

Are there any load pics? Why are there no 100% load pics when it's supposed to work? (taskmanager always around ~10%)
or am I blind?

[informal]

Are there any load pics? Why are there no 100% load pics when it's supposed to work? (taskmanager always around ~10%)
or am I blind?

OMG,it's a conspiracy!!!
Without the captured load bars in task manager we must conclude that AMD demoed unstable chips running at @2V with LN2..:rolleyes:
/sarcasm off

Seriously,the first ES chips(45nm) are shipped to major partners for validation and testing,as of Febr. ...

Here is the load bars at "slightly higher" than 10% mark:
http://www.pcgameshardware.de/screenshots/medium/2008/03/AMD_Phenom_45nm2179.JPG

http://www.pcgameshardware.de/?menu=browser&article_id=634736&image_id=785536

[Periander6]

Check the photo:

http://www.theinquirer.net/gb/inquirer/news/2008/03/05/amd-shows-45nm

About 270mm2.

[Carfax]

From what has been reported, 10-20% on average.

Barcelona -> Shanghai is a bigger move than Conroe -> Penryn. Shanghai has 3X the L3 cache in addition to some core improvements.

Hopefully Shanghai will do what Barcelona was supposed to and run the NB/L3at a HIGHER frequency than the CPU. That alone could improve performance by up to 5-10%.
So in theory Shanghai should be slightly faster than Penryn clock-for-clock but it will get demolished by Nehalem.

Whoa, can you link me to a source?

That would be amazing if AMD could boost Shanghai's performance that high.

I've always wanted to go back to AMD, but unfortunately Barcelona wasn't tempting enough..

If Shanghai performs as reported though, I might just make the jump, then go back to Intel once Nehalem is on 32nm..

*Edit* Nevermind, found a link

[JumpingJack]

Seriously,the first ES chips(45nm) are shipped to major partners for validation and testing,as of Febr. ...


Are you certain? I can understand a demo, but just a last month, AMD was saying 'we expect first silicon in January', first silicon in January to shipping sampling to customers is way way too soon.

[flippin_waffles]

Is DC 2 already implimented in Barcelona, or is that comming in Shanghai?

[JumpingJack]

yeah I was getting confused about fd-soi as Intel did research into that before.

http://www.intel.com/technology/silicon/ieee/soi2000.pdf

I do not recall Intel producing any literature on FD, but they did do a pilot run on PD-SOI, from this they reported the same advantageous gains expected in SOI, but also concluded that it would not scale as well in later nodes:

Another SOI parameter that scales poorly is the history effect
on delay.

100 nm devices described have the best Ion-Ioff characteristics
reported for 0.18 mm generation PD-SOI. SOI inverter delay of
7.4 ps is obtained at Vdd=1.5V and Lgate=100 nm. However, the
expected performance gain for PD-SOI diminishes dramatically
for 50nm devices due to (i) aggressive reduction of junction
capacitance for our bulk CMOS, (ii) the reduced impact of area
junction capacitance with scaling, and (iii) increased history
effect on delay for scaled Vdd

This SOI vs Bulk debate was fought long and hard between Intel and IBM, Intel's argument was the the costs associated with going SOI were not justified, but my opinion is that there were probably also a stack of patents 10 feet high they would have needed to either a) work around or b) coughed up serious licensing dough that they simply stuck with bulk.

In any event, the 130 nm -> 90 -> 65 nm -> 45 nm (this one still a ?) scaling for SOI would appear to have validated thier position on the technical side.

It was a lot of fun watching IBM and Intel jocky and chest thump over this :)

EDIT: Intel is using SOI though for their silicon photonic wave guides : http://www.eetasia.com/ART_8800359416_480200_NT_c75656df.HTM but this is out of complete necessity, you need a completely enclosed cavity to refract the light through the optical path, the burried oxide is needed to completely the enclosure.

[BrowncoatGR]

Is DC 2 already implimented in Barcelona, or is that comming in Shanghai?

Neither. Montreal will be the first MP product to feature HT3

[JumpingJack]

*Edit* Nevermind, found a link

Could you post it please, I would like to read it.

Edit: It isn't this one is it? http://www.fudzilla.com/index.php?option=com_content&task=view&id=5904&Itemid=1


Jack

[JumpingJack]

Wombat it would make those pic a whole lot more usefull if they included a result :)

:) :) :rofl: :rofl: :rofl: I was thinking exactly the same thing.

[Marvin_The_Martian]

Thanks JumpingJack, was a good readup cleared some off my confusion :toast:

Though I can't read the article in your edit, I'll bookmark it and might sign up there tomorrow ( can't be arsed right now )

[JumpingJack]

I highly doubt that CSI in Nehalem will bring anything to the table -compared to Penryn- when desktop is in question.I think that Penryn's high freq. FSB will NOT be slower than CSI I/O we will see in Nehalem,at least in desktops.Also HyperThreading could potentially speed it up a bit in multithreading apps,but still needs to be seen by how much.

No it won't -- much like HT does not do a massive amount for K8/K10 in single socket DT workloads ... what it does do is allows the memory controller to be moved on die... which will provide a big difference. Thus, the memory access path is not in contention with all the other IO that might occur.

EDIT: CSI effective BW though will be much higher though ... http://www.realworldtech.com/page.cfm?ArticleID=RWT082807020032 David did a great job here picking apart Intel patents over the past several years to peice together some of the CSI technical details.

Initial CSI implementations in Intel’s 65nm and 45nm high performance CMOS processes target 4.8-6.4GT/s operation, thus providing 12-16GB/s of bandwidth in each direction and 24-32GB/s for each link [30] [33]. at 1333 Mhz, Intel currenlty provides peak BW of 10.65 GB/sec in one direction only.

[JumpingJack]

Thanks JumpingJack, was a good readup cleared some off my confusion :toast:

Though I can't read the article in your edit, I'll bookmark it and might sign up there tomorrow ( can't be arsed right now )

No problem .. the article in my last edit was just a google on "Intel SOI Silicon Photonics" you will get several links....

[Marvin_The_Martian]

No problem .. the article in my last edit was just a google on "Intel SOI Silicon Photonics" you will get several links....

Took me 5 clicks to get to this (http://www.convergedigest.com/blueprints/ttp03/bp1.asp?ID=242&ctgy=Market)

[JumpingJack]

Yes correct, the real vcore is around 1.3V afaik.

How do you take the Vcore exactly?

[JumpingJack]

Read the post made by CPU-z author,below :) :


Also look at the latest post made by wombat containing pictures of 16 cores machine utilizing Shanghais,now with VCore readings @1.15V.

My point wasn't is it accurate or not, even if it is... it is nothing to worry about or get excited about ... first silicon typically is way below targeted goals, it usually takes 2 or 3 revisions before final/retail silicon makes it.

The milestone here is not did they make a sellable part... the milestone is they show working silicon. This is about 10x more than what they showed for 65 nm ... heck, they launched 65 nm and it was a month or two later before anyone actually saw working silicon. :)

[JumpingJack]

Took me 5 clicks to get to this (http://www.convergedigest.com/blueprints/ttp03/bp1.asp?ID=242&ctgy=Market)

Yeah, in your link they used SOI to build # 2 in the cartoon about 2/3's down the article.

http://www.convergedigest.com/images/bp/TTP/intel-fig2.gif

[informal]

Are you certain? I can understand a demo, but just a last month, AMD was saying 'we expect first silicon in January', first silicon in January to shipping sampling to customers is way way too soon.

From the EEtimes (http://www.eetimes.com/showArticle.jhtml;jsessionid=K5ZL5KTVYNRBMQSNDLRSK HSCJUNN2JVN?articleID=206901553) article(yesterday):

EE Times:
AMD ships 45-nm Shanghai, Deneb chips

Antone Gonsalves
InformationWeek
(03/04/2008 9:00 AM EST)

Advanced Micro Devices on Tuesday said samples of its first 45-nanometer processors have been shipped to computer manufacturers, and the company is on track to start production in the second half of the year.

AMD plans to initially release two quad-core processors, one server chip codenamed Shanghai; and the other a desktop processor codenamed Deneb. AMD's current products are built on an older 65-nm architecture.

[JumpingJack]

From the EEtimes (http://www.eetimes.com/showArticle.jhtml;jsessionid=K5ZL5KTVYNRBMQSNDLRSK HSCJUNN2JVN?articleID=206901553) article(yesterday):

Antone Gonsalves
InformationWeek

Same article same guy, EEtimes reprints articles from around the web:

http://www.informationweek.com/news/showArticle.jhtml?articleID=206901459&subSection=News

I simply think he got his demo/ship mixed up... first silicon in January to shipping samples for validation?? Just seems too early to me. But hey maybe they can skip B3 and go stright to 45 nm shanghai :)

[informal]

Notice how he talks about the same chips(45nm) in the same sentence,at the end of it, and he actually wrote "AMD said..".No mentioning of Barcelona at all.
So to me it looks like early samples of Shanghai\Deneb are really being shipped(in small quant. of course) to some selected partners.This tells us nothing about the state of the chips,BUT it looks like the 0 stepping of C revision is good to run variety of OSes and client apps.

PS BTW its March already,it's been a good month+ or so since they got first batch(the demoed batch) out of the FAb36 and it seems very likely they did ship some chips for testing.

[JumpingJack]

Notice how he talks about the same chips(45nm) in the same sentence,at the end of it, and he actually wrote "AMD said..".No mentioning of Barcelona at all.
So to me it looks like early samples of Shanghai\Deneb are really being shipped(in small quant. of course) to some selected partners.This tells us nothing about the state of the chips,BUT it looks like the 0 stepping of C revision is good to run variety of OSes and client apps.

PS BTW its March already,it's been a good month+ or so since they got first batch(the demoed batch) out of the FAb36 and it seems very likely they did ship some chips for testing.

It could very well be true... AMD could have produced production/sample worthy silicon on the first silicon out. It just seems too soon for me.....

This is such big news, if it were true, the Inq, CRN, Dailytech, just about the whole internet would have lit up..... rather, it appears to me that he confused the info that B3 was shipping to customers as samples (news a few days ago) with a 45 nm demo of first silicon at CeBIT (news yesterday).

Yeah, a month + after first silicon seems about right to demonstrate functioning silicon -- and this is indeed a great milestone, which builds confidence that they will be able to launch before end of year.

EDIT: Charlie is saying the same thing (though I am not a big fan of the Inq, two different sources saying the same thing adds credibility) -- They are at the point now of sampling customers with parts, and claim production for the second half of 2008.
http://www.theinquirer.net/gb/inquirer/news/2008/03/05/amd-shows-45nm
So it would appear I am over analyzing the info ... but I surely would think that sampling parts to customers would have made a bigger headline elsewhere.


Jack