Asus claims PAT can be enabled on P4P800

[RichBa5tard]

http://www.extremetech.com/article2/0,3973,1112152,00.asp

Interesting read. Is this "'Memory Acceleration Mode" really PAT, or just a few other optimisations?

Your opinions? If this is true, why get a P4C...?

[JCviggen]

Originally posted by RichBa5tard
If this is true, why get a P4C...?

Because the P4C has been shown to be the better board, and faster clock for clock than the P4P.... :(

[BrainStorm]

If MAM isn't PAT, why wouldn't ASUS also apply MAM to CW boards to speed them up? Also, if George Alfs from Intel was speaking correctly when he said PAT was merely speed binning the chipsets, then the hardware must be the same and PAT would mostly likely have to be activated through some register settings in the chip.

Which would mean it is possible for ASUS to do what they say, the question is whether the SD chipsets are good enough silicon to handle it. But if it is something you can turn on or off in the bios, then if the SD chipset can't handle it, you just disable it and you're good to go.

I would say we really don't know the answer yet, but I don't see anything that procludes it from being true - at least not yet.

[Liquid3D]

Brainstorm, would mind explaining to me in analogous terms the meaning behind the following statment; "PAT is simply a marketing term for the "bin splits" which produce the various speed grades of microprocessors"

What exactly is "Bin-splitting"? And are there more benefits to PAT then a simple memory bandwidth increase of 3% to 5%?

Thank you.

[BrainStorm]

Originally posted by Liquid3D
Brainstorm, would mind explaining to me in analogous terms the meaning behind the following statment; "PAT is simply a marketing term for the "bin splits" which produce the various speed grades of microprocessors"

What exactly is "Bin-splitting"? And are there more benefits to PAT then a simple memory bandwidth increase of 3% to 5%?

Thank you.

"Bin splitting" just means means they test how fast the chips can work and then sort them according to how fast they are (i.e., they get put into a different "bin" depending on how fast they are). In this case, the fastest chips get to be CW, and the slower chips get to be SD.

Intel and AMD have always done that with processors. You also see it now with memory sticks. This may be no different.

[JeffPH]

Originally posted by BrainStorm
"Bin splitting" just means means they test how fast the chips can work and then sort them according to how fast they are (i.e., they get put into a different "bin" depending on how fast they are). In this case, the fastest chips get to be CW, and the slower chips get to be SD.

Intel and AMD have always done that with processors. You also see it now with memory sticks. This may be no different.

Learned something new today :)

thanks BrainS

[Liquid3D]

OMG I remember learning this term about a year ago. Thank you, I really appreciate your re-educating me. Does this indicate there are NO physical differences between the two NB's? Ergo it's either BIOS version dormant or active? Unless they disable some internal structural component, like on the "fabled" Thorton processor where only half of the 512K cache is used?

If bin splitting is the case, and this really get's Intel's little economic brain going, i wonder if engineers (with cost-control's whip across their backs) will be thinking up some new overclock prevention method for Chipsets as well?

[JCviggen]

Originally posted by BrainStorm
In this case, the fastest chips get to be CW, and the slower chips get to be SD.



with the difference that they enable the PAT shortcut on the CW's ... thats probably the main reason they bin them, PAT will reduce the maximum FSB on any silicon.
I do think that they have more than one "bin" for canterwoods... prolly asking a few $ more for the best ones, enabling slightly higher OC's on some boards.

[Ewok]

Originally posted by JCviggen
with the difference that they enable the PAT shortcut on the CW's ... thats probably the main reason they bin them, PAT will reduce the maximum FSB on any silicon.
I do think that they have more than one "bin" for canterwoods... prolly asking a few $ more for the best ones, enabling slightly higher OC's on some boards.

which might also explain the high price for the P4C compared to other boards, and the seemingly better fsb speeds it gets overall than most of the others.

[macci]

Does this indicate there are NO physical differences between the two NB's?
The 865PE chipset is physically smaller than a 875 chipset. The core is most likely the same thou.

[RichBa5tard]

Originally posted by macci
The 865PE chipset is physically smaller than a 875 chipset. The core is most likely the same thou.

If it's not the exact same size & it's made on the same process (0.15µ?), why would it be the same core? Basically, you're claiming the canterwood has more silicone but equal amount of transistors? That doesn't make sense. :confused:





Hmmmm... is anyone skilled enough to make a P4P800/P4C800 hybrid bios?

[JCviggen]

Originally posted by RichBa5tard
If it's not the exact same size & it's made on the same process (0.15µ?), why would it be the same core? Basically, you're claiming the canterwood has more silicone but equal amount of transistors? That doesn't make sense. :confused:



he means the packaging, not the die itself... that is the exact same size

[Zroc]

Again, 875P is physically different folks. Yes, they speed bin to get the best chip, but then they physically alter 875P's to shave clocks in the memory controller itself.

So yes, they originate from the same silicon, but the final product is different.

[JCviggen]

Originally posted by Zroc
Again, 875P is physically different folks. Yes, they speed bin to get the best chip, but then they physically alter 875P's to shave clocks in the memory controller itself.

So yes, they originate from the same silicon, but the final product is different.


dont those "physical alterations" work only past 200/200 FSB ?

[Liquid3D]

From what I'm gleaning reading about the "die" and the architecture which is imaged upon it, it's perfectly reasonable to assume the same "gate length" can be applied to an infinite number of architectures.

I also beleive the "silicon" can be exactly identical throughout the "fab" with final "physical" adjustments made; "Depending on the package type, the pins or leads may have to be trimmed and formed to the desired shape for use in applications

[Manoj]

http://www.xtremesystems.org/forums/showthread.php?s=&threadid=13790