Intels IMC [Archive] - XtremeSystems Forums

K404

03-15-2007, 03:16 AM

http://www.theinq.com/default.aspx?article=38232

Basically...top-end CPUs only, for the end of next year and it currently look a bit of a mess.

How will an IMC talk to the chipset and RAM?
I`m guessing the traces will join on the way to the RAM which means the IMC has to be the same or very close to the same as whatever NB memory controller Intel have at the time. nVidia chipset support? That looks a mess too- I cant see the IMC matching both Intel and nV controller pin-outs if you see what I mean?

Lower-end parts still use the chipset memory controller....

Well...at least they're thinking about it.

K

FghtinIrshNvrDi

03-15-2007, 06:51 AM

good to see they're trying to get out of FSB land.

Ryan

arisythila

03-15-2007, 06:59 AM

LOL, there so behind AMD......

arisythila

03-15-2007, 07:07 AM

Lol :-)

bloodbanger

03-15-2007, 07:08 AM

LOL, there so behind AMD......

With these kinds of constructive replies i should get 1700 posts too in very short time:slapass:

we already know that you're an AMD-lover(don't wanna use the word fanboy)but you really have to prove that in every thread?

arisythila

03-15-2007, 07:23 AM

Im not an fanboy... With Intel cut out of the picture, I can only buy from AMD or VIA. Until I receive my settlement from Intel. I wont buy from them.

Thats all.

~Mike

Shintai

03-15-2007, 07:30 AM

Well, no desktop, not even XE will have IMC. Also alot of people overestimate the value of an IMC. The IMC is good, but its more like a troublesome kid when you change memory. Also large caches and memory disamguation makes the IMC even less useful. For the DP/MP servers it got a place and need. For the desktop its pure useless and ruins all the flexibility.

FghtinIrshNvrDi

03-15-2007, 07:32 AM

wow... brace for impact.

Ryan

bloodbanger

03-15-2007, 07:35 AM

Im not an fanboy... With Intel cut out of the picture, I can only buy from AMD or VIA. Until I receive my settlement from Intel. I wont buy from them.

Thats all.

~Mike

ah okay i didn't know this...please accept my humble apologies;)

arisythila

03-15-2007, 07:43 AM

ah okay i didn't know this...please accept my humble apologies;)

No problem... Once I receive it, I will buy from Intel again. but maybe not, considering they've dragged this out like a year and 1/2 so far.

~Mike

LOE

03-15-2007, 08:32 AM

LOL. ONLY with the IMC.

IPC they are currently kicking sand in AMD's face. Not until K10 will AMD regain the upper hand.

LOL, are you sharing some new information or just wanted to be a reminder?

fhpchris

03-15-2007, 08:59 AM

LOL. ONLY with the IMC.

IPC they are currently kicking sand in AMD's face. Not until K10 will AMD regain the upper hand.

45nm core 2 duo will hit hard...

Revv23

03-15-2007, 08:59 AM

personally in dealing alot with AMD and Intel i prefer not to have the mem controller..

i prefer the flexibility i get with the northbridge controlling the memory...you can get an upgraded mem controller without having to buy a new chip... when DDR3 matures i can get DDR3 and a mobo and a new cpu later if i want. rather then needing new ram/cpu/mobo all at once. This reminds me of K7... I had K7 for SDR, DDR, then dual channel DDR, same chip. K7 by far was my favorite chip ever, most fun to clock and such great value with a great upgrade path. :)

i can put my e6400 on DDR, DDR2, DDR3, and whatever else. also ODMC in my experience are finicky, so many timings on AMD's i can't stand it, most of them don't do anything, and each controller runs best with different ones... quite annoying. Plus for whatever reasons onboard memory control seems to introduce coldbugs....

So imo, mem controller = added performance and added hassle, if they can get away without it, i prefer that. My opinions don't matter though and it's pretty much inevitable that they will integrate the mem controll...

Maybe if intel gets CSI done right they won't need to integrate it... a high speed low latency interface to the NB might be just as good, could also help intel compete price wise. (yes mobo's are more expensive, so it balances out, but i buy more cpu's then mobo's usually)

NiCKE^

03-15-2007, 09:04 AM

[XC] gomeler

03-15-2007, 09:25 AM

Only a good thing if the IMC on Intel chips DOESN'T bug out at -30 celsius.. I don't want to have to search for golden batch Core4Octo's that won't freeze up when you give them a bit too much loving under the cascade.

arisythila

03-15-2007, 09:33 AM

YEah, I was going to say, I wonder if Intel is going to have a coldbug... Im not 100% sure why AMD had a coldbug.. It doesnt make sense to me.

~Mike

nn_step

03-15-2007, 12:37 PM

LOL. ONLY with the IMC.

IPC they are currently kicking sand in AMD's face. Not until K10 will AMD regain the upper hand.

not to nit pick or anything but Intel's IPC is closely tied to its prefetch logic which may require serious changes to adjust for the new IMC

Spawne32

03-15-2007, 04:15 PM

Im not an fanboy... With Intel cut out of the picture, I can only buy from AMD or VIA. Until I receive my settlement from Intel. I wont buy from them.

Thats all.

~Mike

settlement? for what? were you seriously injured by a intel cpu?!? :confused:

|3ourne

03-15-2007, 04:51 PM

Yupp I've to agree with you. Need to change CPU due to new type of memory is kinda sad, AMD earns on it though since users has to buy more chips but they might loose on it since it's rather annoying.

WAIT !!!!! :eek:

Can .... can... it really be that people are blaming AMD for making money by selling a new product with DDR2 support and now 65nm ?? Tell me something , did you have to buy DDR2 and a new motherboard when LGA775 came out ??? At least with AM2 you are relatively future secure that you only have to buy a K10 processor and not an entire complete system. Hell when you went from Pentium D to Core2Duo , you STILL had to buy a motherboard thats compatible with it ( unless you already had one when Pentium D was out ) . Why is that you guys are suddenly bashing AMD for something that Intel did in the past when you vociferously defended Intel's move then ??? Doesnt it seem like you are coming across a bit as a fan boy ???

LOL. ONLY with the IMC.

IPC they are currently kicking sand in AMD's face. Not until K10 will AMD regain the upper hand.

No new info (thanks to AMD's piss-poor marketing practices of not leaking any benchmarks). Just stating the ASSUMPTION that K10 will have higher IPC.

Dude , I have been following your posts lately and it seems like you have absolutely NOTHING intelligent to offer on these forums. But you are amazing at starting an AMD bashing party. Its alright , we know you have a merom rig and you love it more than your mother and its faster than a ferrari. Now that you are done making sure that everyone on these forums know that , can you please keep your stupid worthless intel biased comments to yourself and actually gain some knowledge about computers for which we all are here anyways ?? Your blind fanaticism has become really annoying when a person starts to read a thread in the News section about Intel's IMC and your comment is " AMD blah blah blah and Intel better ". Dammit , you really got that e-pen1s ego thing going dont you ? :nono:

I am actually happy that Intel is switching over to IMC , because that means no more 250 USD intel motherboards. Removal of IMC from the motherboard lowers the costs immensely and in the end it will be us consumers who will benefit , not to mention the increased efficiency in bandwidth. AMD was the company which brought this tech to our desktops and we got to enjoy massive bandwidths. Intel kept playing in the FSB box and until Core2Duo came out , they were being heavily bottlenecked by the FSB. The sheer speed of C2D nullifies that effect. But C2D will perform possibly even better if it gets an IMC. Meaning good news for us consumers. Whoever is at the top , competition is good , but lame bashing is ludicrous.

|3ourne

03-15-2007, 05:07 PM

Nice FLAMEBAITING, you tool.

Did you ACTUALLY READ my post? I SAID that Intel has the potential to benefit EVEN MORE than AMD from an IMC BECAUSE of their architecture. :stick: :slap:

Go back to your nursery rhymes because what we are talking about here is obviously WAY OVER your head. :fact:

And for the record: I have 6 AMD X2 rigs and 3 Intel C2D rigs. But I GUESS that slipped your mind, huh?

EDIT - and if you THINK I am giving AMD a hard time for not releasing some D@MN K10 benchmarks, you are right. They are doing NOTHING but shooting themselves in the foot on this one. But the way Hector ran Motorola's PPC division into the ground, it doesn't surprise me he is doing this at AMD.

yes i did you dumb fool. And if you took time to read MY post you will realise that I didnt include that post in my quotations of you. That is because I thought of it as a legitimate post and worthy addition to the thread. And about you talking bout something thats way over my head , i really dont think your post count tells how much you know , I have been here longer than you have , I have learnt stuff here longer than you have. Just because I dont repost what I hear other people say doesnt mean I dont know what I am talking about. There are many many people here who actually know alot about a cpu's architecture and most of it they dont learn from press release papers or reviews, but You are not one of them. I DO know what i am talking about, and unlike you , I am not biased either towards AMD or Intel . Both have their fallacies and fortes. Post something constructive about AMD or contribute something better than slander about Hector , maybe , just maybe then I will believe that you actually have 6 X2 systems. Till then you are just a fanboi in my books.

[XC] hipno650

03-15-2007, 05:35 PM

oh imc:D this could mean some big gains for intel if they pull it off well. however i do agree that you may have a limited upgrade path with it. for example i could use my p4 with ddr, ddr2 and soon to be ddr3 which is nice to have that flexibility. however intel ruins that for dual core and newer chips (the only good intel chips:( :D ) by making certain new mobo revisions and voltage modifications. but i will trade performance for flexibility any day.

|3ourne

03-15-2007, 06:11 PM

So what if you have been here longer than me. :stick:

Did you HAPPEN to THINK (I know, asking a WHOLE LOT from you) that arisythila and I MIGHT be friends and that remark that you originally quoted might have been a little inside joke with him?

And I AM NOT BIASED towards AMD or Intel, but just because I have the BALLS to call either company OR FANBOY out on their BS I get labeled an Intel Fanboi. (If this were 2 years ago the Intel TROLLS would be all over my back).

I buy WHATEVER is the fastest rig at the time I need that fits within my budget. For 3-4 years (aside from laptops) that has been AMD. Since last summer that has been decidedly Intel.

If you have ANY FURTHER comments, get the balls to PM me. You call me a fool one more time in the forum and I'm going to pass the issue on to the mods. We will let them deal with your 2yo temper tantrums.

PM sent . Enjoy !!!! :toast: :toast:

Revv23

03-15-2007, 06:31 PM

If anything, I could see Intel's architecture benefiting GREATLY from an IMC. Possibly more than AMD's did.

Why? Here is my reasoning:
C2D has more ALUs and FPUs/SSE than P4 and K8. Even with a LARGE cache and excellent prefetch, the stall rate on the decoders is going to be significant. With reduced latency, these could be far better utilized.

Unfortunately, Intel would probably give back some of the performance gains by reducing the size of the caches (to cut manuf. costs).

i agree, low latency is what makes the C2D faster...it doesn't need huge bandwidth at high latency....

arisythila

03-15-2007, 07:04 PM

Did you HAPPEN to THINK (I know, asking a WHOLE LOT from you) that arisythila and I MIGHT be friends and that remark that you originally quoted might have been a little inside joke with him?

I got your back dawg! I'm ready to :slapass: ...... LOL

For guys that like cars, I would post the following analogy:
AMD took an already efficient 3.0L engine and bored it out and put a supercharger on it to make the overall HP produced from that engine greater.

How about a Turbocharger or two.. two GT2871R would pull a prime in the 1/4 mile.

On a more serious note. What did AMD do that caused the cold bug? Do you guys think that Intel is going to go the same route? I remember something about IMC on AMD procs were made to run at a certain temperature, anywhere below that and they would freak out. Any insight on this?

~Mike

arisythila

03-15-2007, 07:15 PM

So its the type of Silicon they use or something? Or what they mix with the Silicon?

~Mike

[XC] gomeler

03-15-2007, 07:16 PM

To be "coldbugged" at -100 celsius is a huge difference from -30 celsius :-\ You wouldn't see 5GHz x6800's with the -30 celsius limit on the IMC equipped AMD chips. Another thing though, some think that the -127 celsius limit is actually a software limit which causes the CPU to roll over to 128 celsius which would be plausable. I know my DS3 just counts down from zero when it rolls below 0 celsius, perhaps I'll have to test under a cascade and see if it'll "throttle" itself at -100 celsius. Would be hilarious if the budget chips became the desireable chips as they wouldn't have an IMC.

edit: some people have blamed the doped silicon that AMD uses for their coldbug problems, no real way to prove it as I believe these doping technologies were incorporated along with the IMC. My A-XP loved the cold and performed like a P4 but I think this was before the SOI technology so can't make a connection.

Revv23

03-15-2007, 07:20 PM

I got your back dawg! I'm ready to :slapass: ...... LOL

How about a Turbocharger or two.. two GT2871R would pull a prime in the 1/4 mile.

On a more serious note. What did AMD do that caused the cold bug? Do you guys think that Intel is going to go the same route? I remember something about IMC on AMD procs were made to run at a certain temperature, anywhere below that and they would freak out. Any insight on this?

~Mike

for whatever reason, depending on which memory controller your chip has that would determine where the cold bug was at.. (about)

the problem didn't plauge the 130nm chips and not all 90nm chips either.

it was really annoying because the newer the chip typically the worse the memory controller, but the better the clocks... so sweet clocking chips frequently couldn't go high under cold temps.

a similar thing happened with ati cards and memory controllers when the x1800's came out, maybe in the 90nm process something with memory signaling gets messed up....anyways im just speculating trying to give you an idea of whats up...

Shadowmage

03-15-2007, 07:55 PM

What is REALLY interesting if you look at the design of K10 is WHAT is different between it and K8.

I'm going to ignore the (badly needed) upgrades to the FPU/SSE units for the moment, even though they are significant. Instead, what AMD spent a TON of resources on were optimizations to the prefetch and branch prediction circuitries. Now, we don't know what the K8's stall and mis-predicted branches were on most code (*but AMD certainly does) but I would BET that it was significant enough that AMD realized that improving the efficiency of their current design was better (for them at least) than making it wider (which is what they did in K7-K8 and Intel did in CD-C2D).

For guys that like cars, I would post the following analogy:
AMD took an already efficient 3.0L engine and bored it out and put a supercharger on it to make the overall HP produced from that engine greater.

It will be interesting to see if Intel takes a similar tack for the successor to C2D. There is already one GLARING fault in C2D that I would be money they address VERY soon: the inability of the CPU to fuse uops in 64-bit mode, resulting in a 5-7% hit in performance in 64-bit mode versus 32-bit.

Just my 0.02.

The original K10 was a 6-8 issue processor. The new K10 (K8L) is still a 3-issue processor. As processor simulations can tell you, increasing processor issue width is quadratic in cost and something similar to logarithmic in returns. I don't think any major company will increase issue width before they saturate all the other performance options with much better gain/cost ratios.

Kingcarcas

03-15-2007, 10:01 PM

Supercharged 3.0L, dual core K10 just might be worth waiting for:D

zakelwe

03-15-2007, 11:36 PM

PM sent . Enjoy !!!! :toast: :toast:

I hope he enjoys it as much as you did the warning PM I just sent you. If you have been here a long time then I expect you to at least know the forum rules and not break them.

That goes for everyone else in the news section as well who breaks the rules.

Cheers.

Regards

Andy

Carfax

03-15-2007, 11:37 PM

The original K10 was a 6-8 issue processor. The new K10 (K8L) is still a 3-issue processor. As processor simulations can tell you, increasing processor issue width is quadratic in cost and something similar to logarithmic in returns. I don't think any major company will increase issue width before they saturate all the other performance options with much better gain/cost ratios.

Where did you hear that the original K10 was 6-8 issue width?

From what I've read, it would be extremely difficult to make an x86 based processor that could have that high of an IPC, while remaining efficient, from both a performance and TDP perspective.

If AMD was serious about producing such a chip, it's no wonder they cancelled it, because such a chip would have consumed enormous power.

I'm talking 200+ watts..

Carfax

03-15-2007, 11:40 PM

Regarding an ODMC on Intel processors, I don't their desktop processors really need it.

I'd rather have larger, faster caches and better prefetch than an ODMC any day..

An ODMC would help the most on HPC and Enterprise workloads, that require enormous amounts of computing power..

LOE

03-16-2007, 12:27 AM

And for the record: I have 6 AMD X2 rigs and 3 Intel C2D rigs. But I GUESS that slipped your mind, huh?

You begin to sound like a broken record brent, this time you forgot to put 100$ on something

would you mind to explain what exactly makes you think intel chips will benefit more from the IMC
core2 already has much lower latency than pentium and doesn't look bandwidth starved and latency dependent at all
even if they make an IMC it would suck using.. guess what, the good old FSB
the IMC is not intels biggest concern, they need CSI badly

Shintai

03-16-2007, 01:35 AM

largon

03-16-2007, 01:42 AM

Exactly, it's not the IMC Intel needs.
The thing they need is a better interconnect for obvious reasons.

K404

03-16-2007, 01:57 AM

Going back to coldbugged AMD IMC:

Take 2 AMD chips... one bugged and one non-bugged(well....say its totally fine under Dice or mid cascade)

The non-bugged chip will scale slowly with dropping temperatures because its temperature range is quite broad (+50 to -80 say) If you knock 5 degrees off the CPU temp you`ll get next to no boost.

Now for the bugged chip. It WILL respond much faster to small drops in temperature and if you can control the temperatures between idle and load (massive capacity, probs under a chiller) The chip will hit the same speeds (or close to it) as the non-bugged chip when its towards the lower-end of its operating range.

Dont believe me? Try it. A good bugged chip will equal a good non-bugged chip if you use appropriate cooling on them. It comes down to quality of silicon though...Not all C2D for example will do 5.5GHz....

Also take for example the AMD 6000+ results we`re seeing. They`re doing 3.3-3.5 under good (non-chilled air) thats better than my non-bugged Opto 150 under a Mach. Yes I know its different revision silicon but the general point is that depending on the stepping AMD are using you dont need LN2 or cascade to get the great clocks on AMD.

PM me an give me hassle so this thread stays on-topic. I know i`m at least 80% right with this idea, I have unfinished numbers and formula that back me up. :)

nn_step

03-16-2007, 02:05 AM

The original K10 was a 6-8 issue processor. The new K10 (K8L) is still a 3-issue processor. As processor simulations can tell you, increasing processor issue width is quadratic in cost and something similar to logarithmic in returns. I don't think any major company will increase issue width before they saturate all the other performance options with much better gain/cost ratios.

Actually the average IPC for x86 software is under 1.2 instructions/Clock.
Thus in theory you could drop from an 3 issue to a 2 issue with very little performance loss. by the same token you can increase the issue to 16 and it wouldn't seriously improve performance, just make branch prediction harder.
Even the world's Busiest Conroe running at 100% 24/7 will not exceed 62% Processor utilization, unless they are running software written specifically for them.

Carfax

03-16-2007, 02:39 AM

Actually the average IPC for x86 software is under 1.2 instructions/Clock.
Thus in theory you could drop from an 3 issue to a 2 issue with very little performance loss. by the same token you can increase the issue to 16 and it wouldn't seriously improve performance, just make branch prediction harder.
Even the world's Busiest Conroe running at 100% 24/7 will not exceed 62% Processor utilization, unless they are running software written specifically for them.

I wonder what the average IPC for C2D is? It would probably be higher I'd wager.

Micro and MacroOps fusion are significant contributions to Core 2's average IPC..

I'm sure Intel will continue to pursue instruction-fusion technology in the future, as it definitely looks promising.

nn_step

03-16-2007, 02:43 AM

I wonder what the average IPC for C2D is? It would probably be higher I'd wager.

Micro and MacroOps fusion are significant contributions to Core 2's average IPC..

I'm sure Intel will continue to pursue instruction-fusion technology in the future, as it definitely looks promising.

under Ideal conditions or standard?

Dresdenboy

03-16-2007, 03:55 AM

It will be interesting to see if Intel takes a similar tack for the successor to C2D. There is already one GLARING fault in C2D that I would be money they address VERY soon: the inability of the CPU to fuse uops in 64-bit mode, resulting in a 5-7% hit in performance in 64-bit mode versus 32-bit.
I think, a while ago I posted a scientific paper here, where some guys analyzed the effect of Macro-Op fusion, the improved branch prediction and L2 cache sizes in C2D on SPEC CPU.

However, there are multiple reasons for the performance hit (which is already offset by the additional registers and other small advantages in 64 bit mode):

code size increase (thanks to the REX prefixes), thus fetch bandwidth becomes more important - think of the 16B fetch of C2D, and there is also a somewhat smaller L1 I$ hitrate
size of pointers doubles, which also lowers D$ hitrates
no macro op fusion, which might even be less effective, if activated, thanks to the smaller amount of instructions fetched per cycle (the instruction fetch buffer won't help much for code>64B)

So if you fix one of the problems on this list, there are still others left.

arisythila

03-16-2007, 06:42 AM

I hope he enjoys it as much as you did the warning PM I just sent you. If you have been here a long time then I expect you to at least know the forum rules and not break them.

That goes for everyone else in the news section as well who breaks the rules.

Cheers.

Regards

Andy

Andy acts like such a hard ass. LOL More power to you brotha.

Without having an IMC on an intel chip to make an "apples to apples" comparison it is very difficult to say if it is manufacturing technology or chip design that is at the heart of the coldbug problem.

And considering that sub-zero users are the tiniest fraction of users out there, I would not expect the bug to be intentionally addressed anytime soon.

Yeah. I just remember AMD always didn't have such a prominent cold bug. I wonder if there is something like a thermal diode that may cut juice at colder/hotter tempatures.(I have no idea)

for whatever reason, depending on which memory controller your chip has that would determine where the cold bug was at.. (about)

the problem didn't plauge the 130nm chips and not all 90nm chips either.

it was really annoying because the newer the chip typically the worse the memory controller, but the better the clocks... so sweet clocking chips frequently couldn't go high under cold temps.

a similar thing happened with ati cards and memory controllers when the x1800's came out, maybe in the 90nm process something with memory signaling gets messed up....anyways im just speculating trying to give you an idea of whats up...

Yeah, the 130nm chips were clean, and most of the 90nm. It's only until now they are pretty much chopped full of the sniffles. I remember people saying it was the memory control that constituted this. So I figured if AMD is having troubles w/ below zero temps, if Intel will have these problems.

Also wondering wondering what exactly caused these cold bugs.

~Mike

K404

03-16-2007, 06:45 AM

The link Brent put up is pretty good. Material Science and Semiconductor theory of Ops but I covered some of that stuff at Uni so it makes sense and is definately possible.

dinos22

03-16-2007, 06:47 AM

i think intel has shown to xtreme overclockers that we don't need IMCs///////// in fact the only thing they bring is a cold bug and BADLY as well unless they can address that which they probably don't give a :banana::banana::banana::banana: about (as we are not a big chunk of the pie) .......but if we could get IMC based CPUs it would be nice for sure not to have them crapping out at least before -100C :D

duploxxx

03-16-2007, 01:13 PM

LOL. ONLY with the IMC.

IPC they are currently kicking sand in AMD's face. Not until K10 will AMD regain the upper hand.

and it took them 4 years to get there..... getting sand in the face but selling many inferior cpu's just because of the brand name......

from the "hard c2d" launch till now is only 9 months... lets see when k10 arrives. Intel is already scared and giving price drops till mid 2007 and let people who buy systems look like fools....

dinos22

03-16-2007, 02:22 PM

and it took them 4 years to get there..... getting sand in the face but selling many inferior cpu's just because of the brand name......

from the "hard c2d" launch till now is only 9 months... lets see when k10 arrives. Intel is already scared and giving price drops till mid 2007 and let people who buy systems look like fools....

i don't understand the whole resentment towards intel

how is C2D inferior man or Centrino for that matter

what is wrong with price drops.......they all do it

price drops for intel are therefor two things........clear stock for new arrivals ;) or competition

Xmas time will be great as we have some 45nm (fingers crossed) arriving so by the time AMD sorts out their CPUs intel will already be at 45nm running much cooler and at higher frequency plus almost no cold bug compared to AMD...............so which CPU do you think majority of people will choose :rolleyes:

XS Janus

03-16-2007, 03:53 PM

Intel is fast lately and newcomers are heading for a fast start soon, so you figure it out!

PS. I remember once "long ago" reading an article that Intel won't "really need" an IMC till 8core dies? This seems to be holding up just fine. New architecture, an IMC, first for servers as the platforms will probably need it more and they will stabilize all the fluctuations that desktop-home building PC market offers on it

dinos22

03-16-2007, 04:44 PM

Shadowmage

03-16-2007, 10:59 PM

Where did you hear that the original K10 was 6-8 issue width?

From what I've read, it would be extremely difficult to make an x86 based processor that could have that high of an IPC, while remaining efficient, from both a performance and TDP perspective.

If AMD was serious about producing such a chip, it's no wonder they cancelled it, because such a chip would have consumed enormous power.

I'm talking 200+ watts..

That's incorrect I think. The last Alpha chip was 8-issue and was around 125W.

Everyone in the industry knows that AMD used to mainly copy Alpha technology, and K10 was no exception. Here's a bad link but you get the point. Just google.

http://en.wikipedia.org/wiki/AMD_K10

---

Ironically, nn_step is right for once. Issue width is not the issue (ha ha pun) at all. It's usually between 1 and 2. Here's a pretty picture as proof. It's from the paper:

Wrong Path Events: Exploiting Unusual and Illegal Program Behavior for Early Misprediction Detection and Recovery, Armstrong, D.N.; Hyesoon Kim; Mutlu, O.; Patt, Y.N., in MICRO 2004.

This paper has nothing to do with issue width but it was the last presentation that I did. Academics really like to simulate 8-issue processors. I added the color to the graph too, in case you think it looks funny. Ignore the blue bar.

Basic specs of the processor:

Issue Width 8 instr/cycle, out-of-order
Instruction Window 256 entries
Branch Prediction 64K-entry Gshare, 64K-entry PAs w/ 64K-entry selector
Branch Mispr. Latency 30 cycles
L1 D-cache 64KB DM, 2 cycle latency
L1 I-cache 64KB 4-way SA
L2 Cache 1MB 8-way SA, 15 cycle latency
L2 Miss Latency 500 cycles (to main memory)
TLB Size 512 entries

http://img255.imageshack.us/img255/8578/speces9.th.jpg (http://img255.imageshack.us/my.php?image=speces9.jpg)

Fuji

03-17-2007, 12:00 AM

I don't think the whole Intel IMC will be as big a deal as everyone says. It will drastically lower latency which will lead to a performance boost.

But, I doubt it's going to make a night/day performance boost.

Why? When you look at Core 2 performance using DDR400 and DDR2, there was a notable difference, but it wasn't night and day (http://www.anandtech.com/mb/showdoc.aspx?i=2813&p=7)

Thats for desktop.

For server it would help. In two quarters, we'll see the quad core XeonMP come to lift with quad busses. The northbridge on that thing uses a lot of power mainly because it has to handle 4 busses and 8 L2 caches.

When Intel goes CSI with XeonMP, we'll have FBDIMM still, but the lower latency should help the server end. It would also make it a lot more scalable which we like.

Itanium, you have a wider pipe and whatnot whatever we don't care as much about Intel's beloved Itanium.

I think it would help the mobile sector. Raising the FSB raises the TDP of the mobile processor and being that the FSB is low, having an IMC would help.

The addition of the Intel IMC would increase bandwith.

According to the INQ, the XeonMP gets a 4+1 channel FBDIMM controller so we get a lot of bandwith, with one channel for memory raid.

The XeonDP gets dual channel DDR3 (that's a theoretical max of 20 GB/sec), which i wouldn't be surprised if it reached 1.33 GHz by the time Nehalem comes out.

One thing (imo) that the IMC allows for is a smaller cache. If you look at Montecito, you had 24 MB of L3 cache for two cores. The quad version with CSI is supposed to have 24 MB of L3 cache for four cores. That's a pretty hefty reduction.

And less cache means less of the wafer used which we also like.

Nehalem is supposed to be a lot faster then Penryn thanks to tweaks, HT and CSI for certain models. It's the combination of the tweaks that makes it a beast.