View Full Version : PAT's not existing?
EdgarBaba
05-29-2003, 08:51 AM
just looked over at inquirer.. saw this:: http://www.theinquirer.net/?article=9738
quite funny i think..:)
JCviggen
05-29-2003, 09:47 AM
I tend to disagree... but i'm still in the middle of running some tests, i'll report back later.
EdgarBaba
05-29-2003, 10:43 AM
Originally posted by JCviggen
I tend to disagree... but i'm still in the middle of running some tests, i'll report back later. if inquirer is only telling half the truth it wouldn't be the first time..:( maybe it's some technology intel want patented first....:confused: :confused:
saaya
05-29-2003, 03:41 PM
ts when has intel EVER told the truth about anything? :rolleyes:
Holst
05-29-2003, 03:49 PM
875 is faster but I agree that PAT is pretty much a marketing name for optimisations that are "difficult" to explain to the general public.
Ive not done much research but its not all that easy to find the technology behind PAT.... if it is anything quantifiable.
BrainStorm
05-29-2003, 03:55 PM
Yeah...it's interesting what George ALfs said. I made a post about it in the Intel forum, and Zroc clarified a bit. Apparently because the "faster memory controller silicon" is used, it allows the memory controller to use some lower latencies with PIV "C" cpus which, of course improves performance.
However, I've seen some FSB numbers posted with Springdale chipsets that blow away most of the Canterwoods. If we analogize to memory...will there come a point where the higher FSB of Springdale perhaps due to higher memory controller latencies actually provides greater performance?
That seems to me to be an interesting question.
EdgarBaba
05-30-2003, 02:32 AM
Originally posted by BrainStorm
Yeah...it's interesting what George ALfs said. I made a post about it in the Intel forum, and Zroc clarified a bit. Apparently because the "faster memory controller silicon" is used, it allows the memory controller to use some lower latencies with PIV "C" cpus which, of course improves performance.
However, I've seen some FSB numbers posted with Springdale chipsets that blow away most of the Canterwoods. If we analogize to memory...will there come a point where the higher FSB of Springdale perhaps due to higher memory controller latencies actually provides greater performance?
That seems to me to be an interesting question. interesting thoughts there. smart thinking :stick:
saaya
05-30-2003, 03:19 AM
pat is supposed to be a new way the chipset adresses the memory, with one or two operations less that need to be done to retrieve info out of the memo. thats what intel said about pat some weeks ago, now hows that difficult to explain? and how can you call this new way of adressing memory not really existant?
i dont get it :confused:
intel... :rolleyes: