L@@K:Important news on Conroe & 975x chipset !!!

[camouflage]

:eek: Made an important test to check the relationship between FSB and RAM speed.

First I chose 9x400 = 3.6GHz and RAM at 500Mhz - ran a SP1M:

http://img64.imageshack.us/img64/6632/9x400fk5.jpg

Then I chose multi 8 and raise FSB up to 450, now at 8x450 = 3.6GHz and I droped down the RAM speed to 450 - ran SP1M:

http://img119.imageshack.us/img119/2737/8x450eb1.jpg

:confused: So this very strange - exactly the same result !!!

What does that mean? To "steal" 50 MHz from RAM speed and add it to the FSB gives the same result ???

So we all don't need high FSB if we have RAM at high MHz.... ??? :confused:

Anyone with similar experiences ???

:stick:

[freecableguy]

Smart cache Technology and 4MB of L2 make quick work of small data sets like SPI 1M. You will find that the lower DDR speed will quickly lose ground to higher speeds once you start playing with test such as SPI 16M or 32M...not to mention that most real-world applications (and games) don't follow the SPI model at all.... ;)

-FCG

[Nanometer]

Very solid FSB. Can you get the Bus speed to 500? ;)

[sierra_bound]

The other thing to remember is that you can run 1M three times and get three slightly different results.

I don't know why people always diss SuperPi. Number-crunching has always been an essential part of computing. People often forget what the real purpose of Prime95 is. If your PC can't do basic calculations, you might as well forget all the "real world" apps.

[Lestat]

i dont gain hardly anything from 9x412 @ 4-4-4-9 vs 463x8 4-4-4-9
i gain about 1 sec. but thats nothing worth bringing to the table.

let me rephrase that. 463x8 is faster. slightly.


odd though givent that you have the ram at 1000mhz... but if the ram is moving faster than the bus. the bus would be the bottle neck. but im guessing on that one.

try a 1:1 test 400x9 1:1 vs 450x8 1:1

[overcrash86]

just look...

http://wowgame.free.fr/Conroe%20E6600%20ES/Aircool%20Noctua/13.984s%203600Mhz%20RAM%20500Mhz%204-4-3-1%20resize.JPG
http://wowgame.free.fr/Conroe%20E6600%20ES/Gskill%206400%20HZ/Pi%201M%20600Mhz%204-4-3-1%2013.937s-2.JPG

wasn't same result...

[Fred_Pohl]

Running the ram asynchronously results in added latency that tends to offset ram speed gains vs synchronous memory to some degree. In this case, the 4:5 latency penalty appears to equal 50MHz ram clock vs 1:1.

[freecableguy]

Running the ram asynchronously results in added latency that tends to offset ram speed gains vs synchronous memory to some degree. In this case, the 4:5 latency penalty appears to equal 50MHz ram clock vs 1:1.

I wouldn't call the penalty 50MHz....rather I would normalize the number to 100% based on DDR "equivalent speed" so that we can at least make the results comparable. Here's how:

Assuming equal CPU speeds (by using either the 8x or 9x multiplier).

400 FSB w/4:5 ratio = DDR-1000 vs. 450 FSB w/1:1 ratio = DDR-900

...if you want to claim that SPI 1M performance is exactly the same (just because the final numbers are equal doesn't mean performance is equal...check out the individual loops...) this would mean that....

the performance penalty incured by selecting the 4:5 ratio can be clearly calculated as...

[('DDR-1000' - 'DDR-900')/'DDR-1000']*100% = ~10%

by this same line of though...

assume you select a FSB of 700 for DDR-1400 (1:1) using a 6x multi.
CPU = 4.2GHz, memory -> DDR-1400

vs.

FSB of 600 for DDR-1500 (4:5) using a 7x multi.
CPU = 4.2GHz, memory -> DDR-1500

and again assuming that the memory timings were unchanged you should (hypothetically) find that the DDR-1400 performance to be higher as it would require ~10% speed advantage or 0.1 x 1400 = 140MHz (1.54GHz) to make up for the 4:5 memory strap.

-FCG

Edit: correct minor spelling typos

[camouflage]

:D Oh, thank You all - very nice discussion here.

Seems 975x chipset requires some intelligence to understand........ :p:

:toast:

[Fred_Pohl]

A 10% latency penalty for 4:5 strap vs 1:1 strap sounds about right for 1M SuperPi. Close enough anyway. It probably changes quite a bit depending on the app and a multitude of other variables, making any definitive enumeration of the latency penalty almost impossible. Still, 10% seems like a reasonable estimate.

[Lestat]

I wouldn't call the penalty 50MHz....rather I would normalize the number to 100% based on DDR "equivalent speed" so that we can at least make the results comparable. Here's how:

Assuming equal CPU speeds (by using either the 8x or 9x multiplier).

400 FSB w/4:5 ratio = DDR-1000 vs. 450 FSB w/1:1 ratio = DDR-900

...if you want to claim that SPI 1M performance is exactly the same (just because the final numbers are equal doesn't mean performance is equal...check out the individual loops...) this would mean that....

the performance penalty incured by selecting the 4:5 ratio can be clearly calculated as...

[('DDR-1000' - 'DDR-900')/'DDR-1000']*100% = ~10%

by this same line of though...

assume you select a FSB of 700 for DDR-1400 (1:1) using a 6x multi.
CPU = 4.2GHz, memory -> DDR-1400

vs.

FSB of 600 for DDR-1500 (4:5) using a 7x multi.
CPU = 4.2GHz, memory -> DDR-1500

and again assuming that the memory timings were unchanged you should (hypothetically) find that the DDR-1400 performance to be higher as it would require ~10% speed advantage or 0.1 x 1400 = 140MHz (1.54GHz) to make up for the 4:5 memory strap.

-FCG

Edit: correct minor spelling typos


ok that was just way too much for my brain to handle right after a long day at the office.

once again we can always count on FCG to melt our brains with a statistical analysis lol