Heterogeneous Multi-Core Architecture rules the future

[onethreehill]

"The epoch of frequency has gone. “Multi-core, frequency, and micro-architecture” are the new ways to further boost the CPU performance. More Intel multi-core information was given out by Bob Crepps, Intel Microprocessor research assistant.

It is a wrong concept that multi-core wastes more power. Actually, the fact is multi-core can provide a better performance at the same power consumption. For example, we are going to compare with single core and a dual core. If we setting the frequency and the voltage to be 85% of the single core, the power consumption is approximated by 2 x 0.85 x 0.85 x 0.85, which is similar to the single core, yet its performance is multiplied by 1.8 (2 x 0.85). Obviously, multi-core features a better Performance per Watt. By the advance on production, the cost for multi-core has lowered to an accepted range. Same with architecture, multi-core is also the star on the development."

http://www.hkepc.com/bbs/attachments_dir/ext_jpg/s2d-1_ZBOXTnItBz95.jpg

http://www.hkepc.com/bbs/attachments_dir/ext_jpg/hmca-2_PIkAZCCvHPTU.jpg

http://www.hkepc.com/bbs/attachments_dir/ext_jpg/sphw-3_uEVn3mWFJ23T.jpg

http://www.hkepc.com/bbs/attachments_dir/ext_jpg/fgpm-4_GCb2V18EMYtr.jpg

http://www.hkepc.com/bbs/itnews.php?tid=626040

[nn_step]

True for multithreaded applications but for single threaded applications (barring RHT) the max performance is that of the fastest core not the sum of the cores

[WeStSiDePLaYa]

how does 2 cores running at 85% use the same power as one core at 100%? doesnt make sense.

say each core draws 100watts at 2000mhz

so one core at 100%=100watts w/2000mhz

one core at 85%=85watts w/1700mhz

that times two for dual core you get 170watts and 3400mhz(assuming multi threaded)

where as two cores at 100% would be 200watts and 4000mhz,

but its still the same ratio. so where do these numbers come from they have? do they just eat alphagetti and laxatives and put together whatever comes out whole as their slides?

[gOJDO]

your math is wrong.
at lower freqfency, the core needs lower voltage for operation.
I don't remember the original formula to measure power consumation, it is very close to:
Power consumation=Voltage*Voltage*Capacitance*Freqfency
so my Turion needs 1.0v to run at 800Mhz, but it needs 1.45v to run at 1.8GHz.
It spends 7,9W on 1.0v at 800MHz and 35W on 1.45v at 1800MHz.

[WeStSiDePLaYa]

your math is wrong.
at lower freqfency, the core needs lower voltage for operation.
I don't remember the original formula to measure power consumation, it is very close to:
Power consumation=Voltage*Voltage*Capacitance*Freqfency
so my Turion needs 1.0v to run at 800Mhz, but it needs 1.45v to run at 1.8GHz.
It spends 7,9W on 1.0v at 800MHz and 35W on 1.45v at 1800MHz.
if you were to work your math backwards it would even go more to show that their math is wrong.

it is using almost 1/3 less volts, and more than 50% slower clock.

[lm358]

Why don't they just manufacture some CPUs with a few Core 2 core's and a whole bunch of configurable logic (ala FPGA devices wth hard-cores), some fast interconnects, DSP blocks, and make it easy to control in software. Presto, computing revolution for the mainstream :-)

[WeStSiDePLaYa]

Why don't they just manufacture some CPUs with a few Core 2 core's and a whole bunch of configurable logic (ala FPGA devices wth hard-cores), some fast interconnects, DSP blocks, and make it easy to control in software. Presto, computing revolution for the mainstream :-)


effeciency and compatibility. and not to mention intel is already hitting issues feeding their current proccesors with bandwidth.

[angra]

how does 2 cores running at 85% use the same power as one core at 100%? doesnt make sense.


I won't speak for intel or this presentation, but NORMALLY when this type of claim/point is made regarding the importance of mulit-core and exposed-communication architectures, we don't assume a scaling of the cache. i.e. we assume that you trade some cache for larger cores. The huge caches absolutely eat power.

[gOJDO]

if you were to work your math backwards it would even go more to show that their math is wrong.

it is using almost 1/3 less volts, and more than 50% slower clock.
If we setting the frequency and the voltage to be 85% of the single core, the power consumption is approximated by 2 x 0.85 x 0.85 x 0.85, which is similar to the single core, yet its performance is multiplied by 1.8 (2 x 0.85).
The power consumation by two cores with reduced voltage and freqfency compared with the singlecore will be 2 * .85 * .85 * .85 * capacitance = 1.228 * capacitance. The capacitance will remain unchanged in both cases, so the power consumation of the two cores with reduced clock and voltage will be 123%, while the performance that the two cores can offer for multithreded apps will be 2 * .85 = 1.7 or 170%. The power efficiency of the two cores(just the cores) will be 1.7 / 1.23 = 1.38 or 138% compared to the single core.

The trick here is that the cores will use shared cache. With less total cache capacity they will maintain their tasks more efficiently compared to singlecores with own non-shared cache. Less transistors will be used for the cache on the package and the power consumation of the chip will be reduced further. (for example 1MB L2 on the K8 takes 60% die space)
The upcoming desktop used Kensifield and server used Covertown are quad-core that two Conroe and WoodCrest are simply put into a single chip. To reduce the load of FSB, Share Cache will be introduced into future multi-core product.
Also the cores will have independend power and freqfency states, they will not work always at highest freq & clock, which is the case with singlecore when processing multiple tasks with different performance requirements.

At the same time, each core would have independent working voltage and frequency, automatically adjusted depends on the load.