AMD embraces AVX making a new superset with SSE5(256bit support)

[informal]

Original find here.

Link to pdf:
http://support.amd.com/us/Processor_TechDocs/43479.pdf

This is BIG news.AMD is playing it safe this time and it seems that on paper Bulldozer will have one of the Sandy Bridge's main innovation(new 256bit wide instruction set).

edit: it looks like 4 operand instruction support is also there,so another (previously AVX exclusive) advantage of SB is matched by this.<-after edit2: this is an error on my part,SandyB won't support FMA4 nor FMA3(IvyBridge will).Look at edit 2.

edit 2:

To recap,after seeing additional info directly from AMD's devcentral(engineering dept blog) we now know what kind of capabilities wrt instruction set compatibility will be in Bulldozer cores and some info on Sandy Bridge uarch due out in 2010(SandyB won't support FMA at all):

1)As AMD's senior fellow stated in his blog Bulldozer will support: intel AVX version 5(meaning full avx spec support with 256b wide vectors),intel FMA version 3 and new extension set called XOP,CVT16,FMA4(former SSE5 instructions with new VEX decoding that were not covered with AVX v5 but could still be very convenient for HPC computing etc.).
2)While supporting AVX,intel's next tick (Sandy Bridge) won't have FMA support in any form. The FMA3 is reserved and planned for tock,a successor to SandyBridge cores(2011 planned). Sandy Bridge will support 256b wide vectors among other stuff AVX will bring ,but won't have FMA.