**Official DFI LanParty UT P35-T2R Review/Overclock/Guide Thread**

[eva2000]

I doubt it.. still cpu fsb wall will be a factor..

my E6750 GO ES on P5K Deluxe max 495-500FSB... on DFI LP UT P35-T2R still max is 495-500FSB

DFI LP UT P35-T2R: Max FSB E6750 G0 ES

Next is looking at MAX FSB. My E6750 on Asus P5K Deluxe maxed out at 495-500FSB with CPU PLL 1.8v voltage. I suspect this is a cpu FSB wall as it's pretty much the same on DFI LP UT P35-T2R maxing out FSB around 495-500FSB but needing CPU PLL 1.95v since next option below it was 1.75v with clockgen voltage at 3.75v. I could boot into memtest86+ v1.70 at 506FSB but it would hang in test #7 (which might be a good test for max FSB for cpus ? ).

System

• Intel Core 2 Duo E6750 ES - L710A438 G0
• Scythe Infinity with modded mount + 120x25mm Spire 96cfm fan
• Transpiper heatsink NOT installed
• DFI LP UT P35-T2R 8/10 bios flashed from 7/27
• 128MB Gainward FX5200 PCI
• 2GB Crucial Ballistix Tracer PC2-8500 naked modules Green dimm slots
• 80GB Hitachi 7K80 SATA
• LiteON CD-RW
• 700W OCZ GameXStream
• WinXP Pro SP2

7x500FSB 1:1

Single Super Pi 32M needed 2.19v bios set vdimm but dual Super Pi 32M needed 2.27v vdimm



Half way mark for dual 32M


Dual Super Pi 32M complete


Everest Bandwidth & Cinebench R10


Bios Settings Used:

CPU Feature
- Thermal Management Control: Disabled
- PPM(EIST) Mode: Disabled
- Limit CPUID MaxVal: Disabled
- CIE Function: Disabled
- Execute Disable Bit: Disabled
- Virtualization Technology: Disabled
- Core Multi-Processing: Enabled

Exist Setup Shutdown: Mode 2
CLOCK VC0 divider: AUTO
CPU Clock Ratio Unlock: Enabled
CPU Clock Ratio: 7x
- Target CPU Clock: 3500Mhz
CPU Clock: 500FSB
Boot Up Clock: AUTO
DRAM Speed: 333MHZ/667MHZ
- Target DRAM Speed: DDR2-1001Mhz
PCIE Clock: 100Mhz

Voltage Settings
CPU VID Control: 1.4625v
CPU VID Special Add: AUTO
DRAM Voltage Control: 2.19v
SB 1.05V Voltage: 1.15v
SB Core/CPU PLL Voltage: 1.95v
NB Core Voltage: 1.50v
CPU VTT Voltage: 1.40v
Vcore Droop Control: Enabled
Clockgen Voltage Control: 3.75v
GTL+ Buffers Strength: Strong
Host Slew Rate: Weak
GTL REF Voltage Control: Disable
x CPU GTL1/3 REF Volt: 110
x CPU GTL 0/2 REF Volt: 110
x North Bridge GTL REF Volt: 110

DRAM Timing
- Enhance Data transmitting: FAST
- Enhance Addressing: FAST
- Channel 1 CLK fine delay: 14
- Channel 2 CLK fine delay: 14

(values in brackets next to AUTO is what memset sees)
CAS Latency Time (tCL): 4
RAS# to CAS# Delay (tRCD): 4
RAS# Precharge (tRP): 4
Precharge Delay (tRAS): 9
All Precharge to Act: 4
REF to ACT Delay (tRFC): 30
Performance Level: 7
Read delay phase adjust: AUTO
MCH ODT Latency: AUTO
Write to PRE Delay (tWR): 11
Rank Write to Read (tWTR): 11
ACT to ACT Delay (tRRD): 3
Read to Write Delay (tRDWR): 8
Ranks Write to Write (tWRWR): AUTO
Ranks Read to Read (tRDRD): AUTO
Ranks Write to Read (tWRRD): AUTO
Read CAS# Precharge (tRTP): 3
ALL PRE to Refresh: AUTO 4

PCIE Slot Config: 1X 1X
CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled
SATA Spread Spectrum: Disabled

7x500FSB 5:6 divider

Notes:

• With 5:6 didvider tWR and tWTR actually show same values in memset as what's set in bios which differs from 1:1 divider where tWR and tWTR show 1 value below in memset compared to what is set in bios.

Single Super Pi 1M & 32M





Half way mark for dual 32M


Dual Super Pi 32M complete


Everest Bandwidth & Cinebench R10




Bios Settings Used:

CPU Feature
- Thermal Management Control: Disabled
- PPM(EIST) Mode: Disabled
- Limit CPUID MaxVal: Disabled
- CIE Function: Disabled
- Execute Disable Bit: Disabled
- Virtualization Technology: Disabled
- Core Multi-Processing: Enabled

Exist Setup Shutdown: Mode 2
CLOCK VC0 divider: AUTO
CPU Clock Ratio Unlock: Enabled
CPU Clock Ratio: 7x
- Target CPU Clock: 3500Mhz
CPU Clock: 500FSB
Boot Up Clock: AUTO
DRAM Speed: 266MHZ/667MHZ
- Target DRAM Speed: DDR2-1201Mhz
PCIE Clock: 100Mhz

Voltage Settings
CPU VID Control: 1.4375v
CPU VID Special Add: AUTO
DRAM Voltage Control: 2.27v
SB 1.05V Voltage: 1.15v
SB Core/CPU PLL Voltage: 1.95v
NB Core Voltage: 1.53v
CPU VTT Voltage: 1.40v
Vcore Droop Control: Enabled
Clockgen Voltage Control: 3.75v
GTL+ Buffers Strength: Strong
Host Slew Rate: Weak
GTL REF Voltage Control: Disable
x CPU GTL1/3 REF Volt: 110
x CPU GTL 0/2 REF Volt: 110
x North Bridge GTL REF Volt: 110

DRAM Timing
- Enhance Data transmitting: FAST
- Enhance Addressing: FAST
- Channel 1 CLK fine delay: 14
- Channel 2 CLK fine delay: 14

(values in brackets next to AUTO is what memset sees)
CAS Latency Time (tCL): 5
RAS# to CAS# Delay (tRCD): 5
RAS# Precharge (tRP): 4
Precharge Delay (tRAS): 9
All Precharge to Act: 4
REF to ACT Delay (tRFC): 30
Performance Level: 7
Read delay phase adjust: AUTO
MCH ODT Latency: AUTO
Write to PRE Delay (tWR): 11
Rank Write to Read (tWTR): 11
ACT to ACT Delay (tRRD): 3
Read to Write Delay (tRDWR): 8
Ranks Write to Write (tWRWR): AUTO
Ranks Read to Read (tRDRD): AUTO
Ranks Write to Read (tWRRD): AUTO
Read CAS# Precharge (tRTP): 3
ALL PRE to Refresh: AUTO 4

PCIE Slot Config: 1X 1X
CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled
SATA Spread Spectrum: Disabled