msi 790 fx-gd70 thread

[SNiiPE_DoGG]

thanks Entropicity, I will do a latest BIOS update as soon as I buy a new USB stick to flash with (left mine at home when I came to university)

[ridney]

snipe, but you didn't leave flow at home didn't you?

[neoNmaZteR]

Flashed back to V1.5 bios and now it overclocks like a charm
1.5 is my best oc bios this far

Now I need to find a way of cooling the nb and sb a little bit more :p
One question, is it possible to make all the pci-e ports running at x16, I have 3xHD4890 cards and it only runs at x8

[Tony]

The difference between cas7 and cas6 1600 is so small it is not worth adding the extra juice, infact cas8 to cas7 is so small again its just not worth it. 4GHZ CPU needs 2600NB to shine, I actually like 3800MHZ CPU and 2800NB with 1600 7-6-6-24 1T as its so easy with both the 955 I have here and a 64Bit OS....why struggle for higher when all you gain is a better everest bench and games don't see much of an increase.

lets be honest here, CPU's need to jump 400MHZ for you to notice, NB is 200MHZ and ram 400MHZ...when Phenom hits 4400MHZ or so then 2000 ram will shine BUT remember the NB will have to be at 3000+ for it to take advantage of the extra ram speed.

[beta]

new bios with cpu core control

A7577AMS.162 ---> A7577AMS.163

- Support "CPU Core Control" function.
- Modify Dual EC item string and ACC option string.
- Modify code to get better DDR1600 compatibility.

http://www.msi-forum.de/index.php?pa...227#post718227

[mav2000]

Wow....so better ddr3 1600 compatibility also and what the hell is cpu core control?? is it the core v??

[Tony]

bios posted here http://www.ocztechnologyforum.com/fo...925#post436925

[SNiiPE_DoGG]

snipe, but you didn't leave flow at home didn't you?

nono, I have Flow here at school It enjoys my room because the dimensions are rather small but I have an 8,000 BTU AC in the window bout 12 inches from the computer

[Smartidiot89]

1.6b3 looks like the biggest change in a very long time...

Think I am gonna wait for v1.6 then I am settling down

[mav2000]

Looks like it clocks better. Used it for ocing for about half an hour and overall seems more stable on oc.

[beta]

it works great, just like 1.5b4. no improvement in oc for me though

[MadDias]

1.6b3 is THE BIOS!!

i´ve been wating for this over a week
finally i can run my g.skill ripjaws on the 1:4 divider at cl7. i was about to return them because of the incompatibility.
now it´s time to play with those low voltage sticks...

[SNiiPE_DoGG]

hmmmm, I still cant get esata to work with my drive on 1.6b3 - sometimes it boots now, but the drive doesnt show - other times it says HD error on disk 5 and forces me into BIOS - have tried IDE mode and AHCI neither work right.

[Bioshock]

so i decided to try the 1.6b3, and again the same things are happening from anything past 1.51

random lockups even when running stock speeds, and restarting 9 times out of 10 results in nothing but a black screen, or the POST hanging after initializing the cpu

im sticking with 1.51 for good

[Yancey]

Has anybody had any problems with the 1.5v flash I know it has been some issues with the 1.6v flash? Thanks for the help..

[wilflare]

anyone figured what's the CPU Core Control thingum? does it automatically turn off cores that are not in use? -if it is, it's a great way to save on power-

[mav2000]

Core control let's u shut down individual cores on your processor. I can get it to shut down cores but that just makes everything slower. So tried my chip with only one core for pi but it won't work.

[Riska]

It works on mine 965BE i can disable all of them beside core 0

[beta]

wtf... 1.6x didnt last long. 1.71 is here:

msi-forum.de

A7577AMS.163 ---> A7577AMS.171

- Update SB750 CIM code to v5.1.0 RC2

[Oliverda]

I've just got this error message after a sudden reboot. (BIOS: A7577AMS.173)

[Oliverda]

I've just got this error message after a sudden reboot. (BIOS: A7577AMS.173)

Sync Flood: When All Else Fails

In some cases, one or more links in HyperTransport may get into a state where ordinary packets cannot be sent reliably. For example, a device may detect a series of CRC errors which indicates to it that either the external link is broken or, more likely, it may not be synchronized with its neighbor with respect to CRC stuffing in the CAD stream. If this is the case, it can't send new packets; it also can't convey the fault using fatal/non-fatal interrupts because they travel in the same channels as other packets.

Sync flood reports errors that cannot be signalled by other methods. It is roughly analogous to the PCI SERR# (system error) event and has a serious impact on the entire chain. Sync flood packets put the chain into an inactive state pending a warm reset to restore normal packet protocol. The behavior of the device initiating the sync flood is slightly different from the other devices which propagate it. The basic rules are described below.
Device Initiating The Sync Flood

1. The device initiating sync flood must have the SERR# Enable bit in the configuration header Command register set = 1 before it initiates a sync flood for any reason.

2. If the device intends to initiate sync flood for CRC errors, buffer overflow errors, or protocol errors, it must first check the corresponding "flood enable" bits in the Error Handling and Link Control registers.

3. The device which initiates a sync flood sets the Signaled System Error bit in the configuration header Status register, LinkFail bit in its Link Control Register, and the Chain Fail bit in the Error Handling CSR. Note: if all conditions for a sync flood have been met, Link Fail is always set — even if the SERR# enable bit in the configuration header Command register is clear (preventing the sync flood packets from actually being sent.)

Devices Detecting Sync Flood

1. Devices detecting sync flood at a receiver input cease all normal packet transmission on the affected chain.

2. Each device sets the Chain Fail bit in its Error Handling CSR.

3. Each device drives sync packets onto all transmitter interfaces, including back to the device which initiated the flood. This assures that sync is seen on all links on the chain.

Sync Flooding And HyperTransport Bridges

1. Bridges set the Detected System Error bit in the Secondary Status register if they see a sync flood on the secondary bus.

2. Bridges may forward a secondary bus sync flood upstream to the primary bus if the SERR# Enable bit in its PCI Command register is set. This is similiar to the behavior of PCI-PCI bridges when SERR# is detected on a secondary bus. The bridge may optionally convert the secondary bus sync flood to a fatal or non-fatal interrupt on the primary bus.

3. Bridges always propagate primary bus sync floods downstream onto their secondary bus(ses).

Miscellaneous Notes

Flooding Continues Until Reset

Once a device commences the sync flood operation, it must continue until a reset is detected on the affected bus. This assures that the sync flood propagates throughout the chain.

[mav2000]

OK due to a numerous amount of PM's I'm going to break this down as simple as possible in this thread since I'm on this board atm and refer people to this post......

Hey chew, in the bios shots that you posted some time bacck, I am not able to understand why both CPU and CPU VDDV are used. I thought CPU V would be used only for minor adjustments, though I am not able to do that on mine as it starts somewhere around 1.1 or so. So why have you used both.

Secondly I am not able to go above 2400 on the NB. If I change the multi and go to 2600, it will just freeze on windows boot up. Could this be an IMC issue.

Am currently on 3.5 with 1.4Vcore. 2.4NB, 1.2V and ram at 1333 6/6/6.

Thanks in advance. Am using bios version 1.6 odd.

[ridney]

i think he used the cpu voltage to offset the cpu vdd and control the amount of vdroop when on load, not sure though but that is how i configured mine, cpu vdd = cpu v +0.025.

with regards to nb, i think there's a problem with the newer bios clocking them higher with the 720BE because i am also experiencing the same problem. i can't clock the nb higher than 2600mhz from 1.5b7 but with 1.5b1 i can clock it up to 3000mhz

[mav2000]

Ok, I guess that would be it then, but from what I understood, CPU v would be an addition of those two values, but I may be wrong here.

Anyway looks like its time to go back to some older bios and recheck my findings.

[1Kurgan1]

Need some help here. I finally got my new Ripsaw 2000mhz DDR3 and got put put my GD-70 into my tower. I was previously using a DFI LP DK M2RSH and running my AII 240 @ 3802mhz w/1.425v 24/7 and it ran great. But the stability with this board seems pretty bad, I updated to the newest beta bios 1.7b3 and am currently running the same speeds I was before, but no stability at 1.425v, I jammed 1.55v down its throat in anger and it seems a bit better, but still not happy. So I'm wondering what bios you guys suggest as the best OCing bios here, and unlocker as I also have a 720BE.